What is USB 3.0 PHY?
USB 3.0 PHY is a Single-Protocol PHY IP core from Nano Silicon listed on Semi IP Hub. It is listed with support for smic.
Vendor:
Nano Silicon
Category:
Single-Protocol PHY
USB 3.0 PHY
Key features
- Standard PHY interface (PIPE) enables multiple IP sources for USB 3.0 Link Layer
- Supports 5.0 GT=s serial data transmission rate
- Supports 16- or 32-bit parallel interface
- Supports PCLK as PHY output
- Data and clock recovery from serial stream
- 8b/10b encoder/decoder and error indication
- Receiver detection
- Low Frequency Period Signalling (LFPS) transmission and reception
- Supports transmitting LFPS when power state changes
- Selectable TX margining
- Compliant with USB 3.0 specification
- TSMC 28/TSMC 40/SMIC 40/SMIC 0.13 nm processes
Block Diagram
USB3 block diagram
Benefits
- All USB devices
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 40nm | 40nm 400 nm | — |
Specifications
Identity
Part Number
USB3
Vendor
Nano Silicon
Type
Silicon IP
Standards & Interfaces
Supported Standards
USB 3.0
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Australia
Frequently asked questions about Single-Protocol PHY IP
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.