What is MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY?
MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY is a MIPI IP core from T2M GmbH listed on Semi IP Hub.
Vendor:
T2M GmbH
Category:
MIPI
MIPI DSI Transmitter v1.2 Controller IP, Compatible with MIPI D-PHY & C-PHY
MIPI DSI transmitter IP is used to connect to up to two displays using the MIPI DSI-1 protocol.
Overview
MIPI DSI transmitter IP is used to connect to up to two displays using the MIPI DSI-1 protocol. It supports video and command displays and can work in dual-display mode. Up to 4x 1.5Gbps D-PHY data lanes are supported. DPI and DBI are fully supported. DSI link can be switched from one mode to another (command to video or vice-versa) without resetting the IP. The behavior of this block is controlled via registers programmed using an APB interface (AMBA 3 compliant).
Key features
- MIPI Alliance Specification for Display Serial
- MIPI display type 1, type 2, type 3 and type 4
- Video mode (Non-Burst with Sync Pulses, Non-Burst with Sync Events and same for Burst mode).
- TE feature (Tearing Effect) for command display
- Power consumption modes (PLL on/off, D-PHY ULPS, optimized mode)
- Supported display sizes: QQVGA (160 x 120) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
- QCIF (176x144), QCIF+ (176x208 and 176x220) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
- QVGA (320x240) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
- CIF (352x288), CIF+ (352x416 or 352x440) -15/20/30/60 fps - 16-18 and 24 bits per pixels
- 1/2 VGA (320x480) and 2/3 VGA (640x320)-15/20/30/60 fps - 16-18 and 24 bits per pixels
- VGA (640x480) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
- WVGA (800x480 - 848x480 -854x480 -852x480) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
- SVGA (800x600) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
- XVGA (1024x768) - 15/20/30/60 fps - 16-18 and 24 bits per pixels
- Main interfaces: MIPI D-PHY PPI, APB system bus interface, 32-bit APB interface registers
Block Diagram
MIPI DSI Tx v1.2 Controller IP block diagram
What’s Included?
- The MIPI DSI Tx Controller interface is available in Source and netlist products.
- The Source product is delivered in plain text Verilog. If needed VHDL, SystemC code can also be provided.
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
Specifications
Identity
Part Number
MIPI DSI Tx v1.2 Controller IP
Vendor
T2M GmbH
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Germany
Frequently asked questions about MIPI IP cores
How should engineers evaluate this MIPI?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this MIPI IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.