Cadence provides a comprehensive solution to address Arm® AMBA® Adaptive Traffic Profiles (ATP) specification.
- Verification IP
Protocol Bridge IP cores enable communication between subsystems inside complex SoCs and ASICs in modern SoC and ASIC designs.
These IP cores support translation between on-chip communication standards and subsystem interfaces within heterogeneous architectures, helping designers scale internal bandwidth, subsystem interoperability, and architectural flexibility
This catalog allows you to compare Protocol Bridge IP cores from leading vendors based on bandwidth, latency, scalability, and process node compatibility.
Whether you are designing mixed-protocol SoCs, legacy-to-modern integration, controller fabrics, or subsystem interconnects, you can find the right Protocol Bridge IP for your application.
Cadence provides a comprehensive solution to address Arm® AMBA® Adaptive Traffic Profiles (ATP) specification.
Cadence provides a mature and comprehensive Verification IP (VIP) for the Peripheral Bus (APB) specification, which is part of th…
Cadence provides a mature and comprehensive Verification IP (VIP) for the AHB specification which is part of the Arm® AMBA® famil…
PCI Express to AMBA 4 AXI/3 AXI Bridge
The IP for PCI Express® to ARM® AMBA® 3 AXI/4 AXI Bridge enables designers who use the AMBA 3 AXI or 4 AXI interconnect on-chip b…
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and ot…
Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs.
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semicondu…
Peripheral Bus (APB) is one of the Microcontroller Bus Architecture (AMBA) family protocols.
GLink (GLink-fs 2.x + PCS-replay) CXS-Bridge is a digital IP to interconnect between two dies that use Glink as a physical layer …
GLink (GLink-fs 2.x + PCS-replay) AXI Wrapper is a digital IP designed to support AMBA AXI3/AXI4 compliant bus of user interface …
The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI…
Multiprotocol IoT gateway is a feature-rich, software only, hardware independent solution, which supports multiple industrial pro…
AXI Bus Functional Model (BFM)
The ability to purchase AXI BFM has been discontinued as of December 1, 2016.
The AXI VIP can be used to verify connectivity and basic functionality of AXI masters and AXI slaves with the custom RTL design f…
AXI Stream Verification IP (VIP)
The AXI Stream VIP can be used to verify connectivity and basic functionality of AXI Stream masters and AXI Stream slaves with th…
AXI Sideband Formatter Utility
The Xilinx® LogiCORE™ AXI Sideband Formatter Utility is used to insert and recover sideband information onto the AXI USER signals…
Converts Avalon Master Endpoints to AXI for seamless interconnection and integration
As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…
As stated by the CSIX Forum, the CSIX standard defines the physical and message layers of the interconnect between traffic manage…
The Xilinx® LogiCORE™ IP Debug Bridge core is a controller which provides a mechanism to establish a communication channel for de…