Trusted Autonomy with Cadence Super Agents & NVIDIA Open Agent Safety Platform
Cadence AI Super Agents bring engineering trusted autonomy to semiconductor workflows, enabled by NVIDIA Open Agent Safety Platform.
Vendor:
Cadence Design Systems, Inc.
Category:
Protocol Bridge
Simulation VIP for AMBA ATP
Cadence provides a comprehensive solution to address Arm® AMBA® Adaptive Traffic Profiles (ATP) specification.
Overview
Cadence provides a comprehensive solution to address Arm® AMBA® Adaptive Traffic Profiles (ATP) specification. The ATP functionality is implemented as a stand-alone SystemVerilog UVM layer fully compatible with Cadence AHB, ACE/AXI, and CHI Verification IPs.
The ATP SV UVM layer includes ATP virtual sequences as well as virtual FIFO fill and drain logic which allows users to manage the requested traffic bandwidth. The ATP UVM layer allows users to specify desired traffic profile properties in the terms defined in AMBA Adaptive Traffic Profiles (ATP) specification. The ATP UVM layer resides over Cadence AMBA VIPs and automatically translates traffic profiles defined by users to the corresponding AHB, AXI, ACE, or CHI protocol traffic.
Supported specification: AMBA® Adaptive Traffic Profiles Specification Issue A.
Key features
- Definition of Adaptive Traffic Profiles
- Definition of write and read traffic profiles using the ATP specification terminology
- Timing Control
- Support of primary and secondary timing parameters
- FIFO Model
- Built-in FIFO logic for managing the traffic bandwidth
- Synchronization Between Traffic Profiles
- Built-in mechanism to coordinate traffic profiles issued from multiple interfaces
- Supported Protocols
- AMBA AHB, AXI, ACE, and CHI protocols
Block Diagram
Simulation VIP for AMBA ATP block diagram
Specifications
Identity
Part Number
Simulation VIP for AMBA ATP
Vendor
Cadence Design Systems, Inc.
Type
Verification IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
Learn more about Protocol Bridge IP core
Cadence Collaborates With TSMC to Deliver Certified Tool Solutions and Industry-Leading, Silicon-Proven UALink IP on TSMC Advanced Processes
Expanded partnership spans TSMC A14 certification, silicon-proven IP on TSMC N3P/N2P, wafer-scale 3D-IC for hundreds of chiplets, and agentic AI flows
Cadence Expands ChipStack AI Super Agent with a New Agent for RTL Generation and Early PPA Optimization
New AI agent leverages core EDA technologies to both create RTL from specifications and upgrade RTL with signoff‑grade quality and performance, validated in early trials with Honda
Cadence Tensilica IP Powers Analog Devices’ Next-Generation DSP Architecture
The joint effort brings Cadence’s highly optimized Tensilica DSP architecture into the next-generation ADSP product family from ADI, enabling richer audio experiences, enhanced voice interactions, and greater system intelligence for future automotive platforms.
Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance
Complete x8 subsystem solution in TSMC N3 process demonstrates industry readiness for mass production and de-risks adoption for AI/HPC customers
DDR5 MRDIMM Gen2: The Missing Link in Scaling AI Infrastructure
Cadence leads the market with its DDR5 MRDIMM 12.8 Gbps Gen2, TSMC N3P IP system solution, establishing a new benchmark for industry-leading PPA. Key industry leaders have already adopted this solution, which is now also available in the TSMC N2P and N5/N4P process nodes.
Frequently asked questions about Protocol Bridge IP cores
What is Simulation VIP for AMBA ATP?
Simulation VIP for AMBA ATP is a Protocol Bridge IP core from Cadence Design Systems, Inc. listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.