AI-Generated UVM Testbenches from SoC Specifications
This article explains why building testbenches by hand is so slow, why the specification is the right place to start, and what an AI-generated flow looks like in practice.
Vendor:
Agnisys, Inc.
Category:
Protocol Bridge
TileLink Target
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and ot…
Overview
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. TileLink is intended for use in a System On-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complicated devices, utilising a fast, scalable interconnect that provides both low latency and high-throughput transfers.
Key features
- TL-UL both 1.7 and 1.8 standard
- TL-UL: 'PutFullData', 'PutPartialData', 'Get', 'AccessAck', 'AccessAckData' and Error response
- All three messages above, with and without latency transaction
What’s Included?
- Agnisys provides a tool - IDesignSpec to configure the IP.
Specifications
Identity
Part Number
TileLink Target
Vendor
Agnisys, Inc.
Type
Silicon IP
Provider
HQ:
USA
Learn more about Protocol Bridge IP core
How IDS-AI Helps Make Your Specifications Golden
Discover how IDS-AI simplifies specification checking to create Golden Specifications and generate reliable outputs for your SoC and IP development workflows.
How to Make Your Specifications Golden
Learn how to create golden specifications for SoC and IP designs with IDS-AI by ensuring completeness, accuracy, consistency, traceability, and faster design automation.
Mastering Semiconductor Chip Design: Tools, Techniques, and Best Practices
Explore how EDA tools and specification automation simplify chip design, verification, software development, and SoC validation while improving quality.
Agnisys and Axiomise Collaborate to Accelerate NoC Design and Formal Sign-off
Agnisys and Axiomise partner to pair IDS-NoC™ automated NoC generation with nocProve® formal verification for AI, GPU, and inference chip designs.
Automated, Faster Specification to Sign-Off with IDS-AI
IDS-AI is the industry’s first agentic AI framework built specifically for semiconductor development. It understands your design functional specification, your control and status registers (CSRs), your programming sequences, your system-on-chip (SoC) hierarchy, and your block interconnections.
Frequently asked questions about Protocol Bridge IP cores
What is TileLink Target?
TileLink Target is a Protocol Bridge IP core from Agnisys, Inc. listed on Semi IP Hub.
How should engineers evaluate this Protocol Bridge?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.