Overview
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. TileLink is intended for use in a System On-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complicated devices, utilising a fast, scalable interconnect that provides both low latency and high-throughput transfers.
Learn more about Protocol Bridge IP core
Modern System-on-Chip (SoC) designs are becoming increasingly complex as they integrate multiple processors, accelerators, memory subsystems, and peripherals. Ensuring efficient communication between these components requires a robust set of interface IPs, interconnects, and protocol bridges. However, designing and integrating these components manually can significantly increase development time, integration challenges, late‑stage bugs, and pressure on already‑stretched engineering teams.
Understand the role of the UCIe D2D Adapter in enabling reliable, scalable, multi-protocol die-to-die communication for chiplet architectures.
Script/simulation approach speeds SoC verification
This whitepaper summarizes the limitations of traditional bus-based approaches, introduces the advantages of the generic concept of NoC, and provides specific data about Arteris’ NoC, the first commercial implementation of such architectures
Synthesizable verification IP speeds design cycle
Synthesizable Verification IP
