The Universal Serial Bus Device controller (GRUSBDC) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
- USB
- Production
- Now
- UTMI, UTMI+ or ULPI
High-Speed Serial IP cores enable the high-bandwidth connectivity required by modern SoCs, AI accelerators, networking equipment, storage systems, telecom infrastructure, aerospace platforms, and data center devices. These IP solutions provide reliable, standards-compliant communication between chips, boards, systems, and external networks.
This catalog includes IP cores supporting industry-standard protocols such as PCI Express, CXL, Ethernet, USB, Fibre Channel, SAS, InfiniBand, Interlaken, JESD204, Optical Transport, CPRI, RapidIO, UniPro, CoaXPress, SpaceWire, and other high-speed serial interfaces. Solutions may include PHYs, controllers, protocol stacks, subsystem IP, and verification components.
Compare high-speed serial IP offerings from multiple vendors based on supported standards, data rates, feature sets, protocol compliance, silicon efficiency, and target applications to identify the right connectivity solution for advanced ASIC and SoC designs.
The Universal Serial Bus Device controller (GRUSBDC) provides an interface between an USB 2.0 bus and an AMBA-AHB bus.
Virtex-5 FPGA, Gen1 PCI Express The Xilinx Endpoint solution for Gen PCI Express® includes a PCI Express 1-lane, 4-lane, and 8-la…
Spartan-3 LogiCORE Endpoint PIPE for PCI Express (PCIe)
Version 1.8 Now Supports Spartan™-3/3E/3A The Xilinx Spartan-3 LogiCORE™ Endpoint PIPE for PCI Express® (PCIe®) protocol layer co…
Reduced Media Independent Interface (RMII)
The MII to RMII LogiCORE is a "shim" core which converts a traditional 16-pin Media Independent Interface (MII) on a Xilinx 10/10…
Included in EDK at no additional charge The Ethernet Lite MAC (Media Access Controller) is designed to incorporate the applicable…
InfiniBand Transport Layer Cores
Polybus offers a family of InfiniBand Transport Layer Cores for use in Data Acquisition, High Performance Computing and Networkin…
FireLink IEEE1394b Link Layer Controller
The synthesizable IEEE1394b Link Layer Controller Core, FireLink®, is based on the Link Layer Controller that has been used for s…
The LogiCORE™ CPRI IP core is a high-performance IP solution that implements the Common Public Radio Interface (CPRI).
The Xilinx Universal Serial Bus 2.0 High Speed Device with Advance Micro controller Bus Architecture eXtensible Interface (AXI) e…
1.06/2.125/4.25 Gbps Fibre Channel and Backplane SerDes
IP
Virtex-5 Endpoint Block Plus Wrapper for PCI Express (PCIe)
Xilinx provides the ability to configure the FPGA Built-in Endpoint Block for PCIe available in Virtex-5 FPGAs.
Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper
The CORE Generator™ Virtex®--5 Embedded Tri-mode Ethernet Media Access Controller (MAC) Wrapper automates the generation of HDL w…
64-bit Initiator/Target for PCI
The LogiCORE™ IP 64-bit Initiator/Target for PCI™ enables designers to build a customized 64-bit, 66 MHz system that performs at …
The HiGig™ MAC transmits and receives data between a host processor and a HiGig™ / Ethernet network that enables networking custo…
Tri-Speed Ethernet MAC Core IP
The Tri-Speed Ethernet Media Access Controller (TSMAC) IP core can be configured to operate in either the Gigabit mode (1000Mbits…
Aliathon’s VT/TU Mapper performs the insertion and extraction of PDH signals into or from multiple VT/TU paths.
Polybus offers a family of InfiniBand Link Layer Cores ranging from a Single Data Rate 4X core (10GBit/Second) to a Quad Data Rat…
XPS_LL_TEMAC Ethernet core provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 …
USB 1.1 Device, Software Based Enumeration (USB11SR)
The USB 1.1 Device, Software Based Enumeration IP Core is RAM based USB 1.1 device core with 32-bit Avalon interface.
32-bit Initiator/Target for PCI Single Project Spartan Series
32-bit Initiator/Target for PCI™ Single Project Spartan® family enables designers to build a customized 32-bit system running at …