Overview
Free LogiCORE™ IP design enabling the use of multi-gigabit transceivers for Xilinx FPGA
Aurora is a LogiCORE™ IP designed to enable easy implementation of Xilinx transceivers while providing a light-weight user interface on top of which designers can build a serial link. Aurora 64B/66B is a scalable, lightweight, link-layer protocol for high-speed serial communication. The protocol specification is open and available upon request. The IP is free to use from the IP Catalog on Xilinx silicon devices.
Aurora is typically used in applications requiring low-cost, high data-rate, scalable and flexible means to build a serial data channel. Its simple framing structure can easily be used to encapsulate data from existing protocols, and its electrical requirements are compatible with commodity equipment. Aurora can be used to provide increased performance without high FPGA resource costs, software redevelopment, or exotic physical infrastructure.
Learn more about Ethernet IP core
In this article, we’ll review the feature set of Ethernet MAC blocks in Virtex-5 devices. We’ll also describe the differences between Virtex-5 and Virtex-4 FX Ethernet MACs, illustrate some potential applications, and describe how to use standard Xilinx tools to integrate an Ethernet MAC into your design.
The fast track development and 24x7 operations have put tremendous pressure on the servers, networking systems and communication equipments. It has become necessary that these systems should operate reliably irrespective of the change in external operating environment like the temperature, humidity, and power fluctuations or, on chip conditions like on-chip temperature, internal voltage levels etc. Measuring the reliability of these physical systems is must for every operational unit.
Flexible FPGA fabric, embedded multi-gigabit transceivers, and off-the-shelf IP enable robust, high performance, and high-integration serial backplane interface solutions
Building on its High-Speed Ethernet controller IP family, Cadence provides ESUN-ready controller IP for next-generation AI scale-up networking.
This blog post explores how the team verified a 10BASE-T1S automotive ethernet subsystem using a Cadence tools-based multi-platform verification, which unifies simulation, emulation, and formal verification techniques.
Learn how ESUN enhances Ethernet for lossless, predictable AI scale-up networking—cutting overhead, reducing tail latency, and improving efficiency.
