Overview
Xilinx provides the ability to configure the FPGA Built-in Endpoint Block for PCIe available in Virtex-5 FPGAs. In addition to configuring the block, the core also provides all of the supplemental logic required to deliver a complete Endpoint solution for PCIe. This Xilinx Endpoint Block Plus Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint applications are available at no additional cost. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other Xilinx connectivity solutions helps customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces. All registered ISE users can request a license file by clicking the “Get License” button on this page.
Learn more about PCI Express IP core
Currently dominating the desktop PC motherboard and graphics markets, the PCI Express protocol is poised to supplant PCI and PCI-X interface as the dominant high-bandwidth interconnect for the server, enterprise, mobile, workstation, networking, communica
Increasingly, FPGA designs are no longer just the 'glue logic' of the past; they are becoming more complex every year, often incorporating challenging such as PCI Express cores. Time spent trying to maintain timing in these modules is not only frustrating, but often unproductive as well. The design preservation flow solves this issue by allowing the customer to meet timing on the critical module(s) of the design and then reuse the implementation results in future iterations.
Geeta Arora, Cadence
Madhumita Sanyal, Synopsys