Uncompromised Graphics Performance Play games for longer First-generation Valhall-based graphics processing unit (GPU) for the pr…
- GPU
Graphics and Vision IP cores provide the hardware acceleration engines required for image processing, video analytics, visual computing, and display management in advanced SoC and ASIC designs.
This category includes GPU, ISP (Image Signal Processor), Video Processing, Display Controller, Image Conversion, and Vision Subsystem IP cores. These solutions enable functions such as graphics rendering, image enhancement, video encoding and decoding, color space conversion, display management, camera processing pipelines, and real-time computer vision acceleration.
This catalog allows semiconductor engineers to evaluate and compare Graphics and Vision IP solutions from multiple vendors based on supported video standards, image quality, AI vision capabilities, throughput, latency, power consumption, silicon area, and process node compatibility.
Whether developing automotive ADAS platforms, AI-enabled edge devices, smart cameras, industrial vision systems, AR/VR applications, mobile processors, or multimedia SoCs, engineers can identify the Graphics and Vision IP cores best suited to their performance, power, and integration requirements.
Uncompromised Graphics Performance Play games for longer First-generation Valhall-based graphics processing unit (GPU) for the pr…
The Arm Mali-D77 is the second-generation premium display processor based on the Komeda display architecture.
The JPEG IP is basically split into the following variants: L2 dual pipe simultaneous encoding for high quality YUV422, for examp…
Customizable Display Controller IP
CDC is a fully Customizable Display Controller IP supporting up to 16k resolutions (4096x4096 pixel) on a MIPI-DPI compliant para…
The Xilinx LogiCORE™ IP Gamma LUT core provides an optimized hardware block for manipulating image data to match response of disp…
The Xilinx LogiCORE™ IP Sensor Demosaic core provides an optimized hardware block that reconstructs sub-sampled color data called…
The Xilinx® LogiCORE™ IP H.264/H.265 Video Codec Unit (VCU) core for Zynq UltraScale+ MPSoC devices is capable of performing vide…
Video Frame Buffer Read and Video Frame Buffer Write
The Xilinx® LogiCORE™ IP Video Frame Buffer Read and Video Frame Buffer Write cores provide high-bandwidth direct memory access b…
Lossless & Near-Lossless JPEG-LS Encoder
The JPEG-LS-E core implements a efficient, low-power, lossless and near-lossless image compression engine that is compliant to th…
Lossless & Near-Lossless JPEG-LS Decoder
The JPEG-LS-D core implements a efficient and low-power, lossless and near-lossless image decompression engine that is compliant …
Phoenix is a programmable HDR Image Signal Processor (ISP) solution.
The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors,…
The Deinterlacer IP core converts input video stream from interlaced format into progressive format and uses bob, intra and inter…
Color Space Converters (CSC) are used in video and image display systems including televisions, computer monitors, color printers…
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size.
The Xilinx® LogiCORE™ IP Video Mixer enables users to mix video layers.
H.264 High 10 Intra Profile Encoder
The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard.
Cost Efficient and Low-Power Design for MCUs, Wearables, and AIoT Devices
Motion JPEG Over IP – HD Video Encoder Subsystem
This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of motion JPEG…
Hardware RTP Stack for JPEG Stream Encapsulation
Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates JPEG streams to RTP packets compliant with RFC 2…