Hardware RTP Stack for H.264 Stream Encapsulation
Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates H.264/NAL streams to RTP packets that are compli…
- H.264 / AVC
Graphics and Vision IP cores provide the hardware acceleration engines required for image processing, video analytics, visual computing, and display management in advanced SoC and ASIC designs.
This category includes GPU, ISP (Image Signal Processor), Video Processing, Display Controller, Image Conversion, and Vision Subsystem IP cores. These solutions enable functions such as graphics rendering, image enhancement, video encoding and decoding, color space conversion, display management, camera processing pipelines, and real-time computer vision acceleration.
This catalog allows semiconductor engineers to evaluate and compare Graphics and Vision IP solutions from multiple vendors based on supported video standards, image quality, AI vision capabilities, throughput, latency, power consumption, silicon area, and process node compatibility.
Whether developing automotive ADAS platforms, AI-enabled edge devices, smart cameras, industrial vision systems, AR/VR applications, mobile processors, or multimedia SoCs, engineers can identify the Graphics and Vision IP cores best suited to their performance, power, and integration requirements.
Hardware RTP Stack for H.264 Stream Encapsulation
Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates H.264/NAL streams to RTP packets that are compli…
Video and Image Processing Pack
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Video edge detection is the process of calculating gradients (rates of change) in pixel values in an incoming frame.
Gamma correction is a type of pre-distortion correction made to images or video frames to offset the non-linear behavior of displ…
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
The XPS Thin Film Transistor (TFT) controller is a hardware display controller IP core capable of displaying 256k colors.
The Video Timing Controller LogiCORE IP is a general purpose video timing detector and generator.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Color Filter Array Interpolation
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
YCrCb to RGB Color-Space Converter
The Xilinx YCrCb to RGB Color Space Conversion LogiCORE™ is an optimized hardware block for converting YCrCb video data to the RG…
RGB to YCrCb Color-Space Converter
The Xilinx RGB to YCrCb Color Space Conversion LogiCORE™ is an optimized hardware block for converting RGB video data to the YCrC…
Versatile Video Input - frame grabber
The logiWIN Versatile Video Controller is a picture process unit that accepts versatile video input streams, converts them to the…
NTSC/PAL Adaptive 3D Comb Filter and Noise Reducer
Implemented in approximately 50,000 gates, the AVQ3000 is a silicon-efficient, high-quality solution for video decoding, noise re…
D/AVE 2D is a 2D GPU Hardware IP Core, optimized for easy integration into FPGAs and ASICs.
GPU silicon IP with a software ecosystem that you can license, customize, and tape out. Designed to scale from chiplet to SoC to electron-to-token systems (ETMsTM).
High-performance image enhancement for moving-camera systems
4K/8K Multiformat IP supporting AV2 decoder
Multi-standard video codec hardware IP that supports a wide range of video codec standards, including AV2, AV1, VVC, HEVC/H.265, AVC/H.264, and VP9