D-PHY physical layer
- MIPI D-PHY
- TSMC
- 7nm
- N7+
- Silicon Proven
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
D-PHY physical layer
HDMI 1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 65/55GP
A single-port IP core called the HDMI receiver PHY (Physical layer) is completely compliant with HDMI 1.4's specifications.
HDMI 1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 65/55GP
Physical layer IP core for HDMI transmitters that complies exactly with HDMI 1.4 specifications The HDMI transmitter PHY provides…
LVDS 160MHz 8-Lane PHY TX IP on TSMC 16FFC
The CL12491M8TIP160 transmitter converts parallel RGB data and 4bits of HYNC,VSYNC,DE and Control) of CMOS parallel data into ser…
SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC
The CL12811M8TIP10000 TXPHY supports 8 TX DATA lanes for up to 10Gbps application.
Camera Receiver - 10.0Gbps 8-Lane - TSMC 12FFC
The CL12812M8RIP10000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and D…
Camera Receiver - 5.0Gbps 8-Lane - TSMC 12FFC, 6FFC
The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DS…
This specific IP macro is designed in TSMC 4nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
The ODT-UCIE-UNI-TX-16GXX-16FFCT is a low power D2D transmitter IP in TSMC 16FFC process.
Ultra-Low Latency 32Gbps SerDes IP in TSMC 12nm FFC
As real-time workloads—from high-frequency trading to low-latency AI and edge analytics—push system responsiveness to the limit, …
Ultra-Low Latency 32Gbps SerDes IP in TSMC 22nm ULP
As real-time workloads—from high-frequency trading to low-latency AI and edge analytics—push system responsiveness to the limit, …
As the demand for higher data rates and increased serial I/O density intensifies, the performance requirements for next-generatio…
32G PHY in TSMC (N5A, N3A) for Automotive
The multi-lane Synopsys Multi-Protocol 32G PHY IP is part of Synopsys’ high-performance multi-rate transceiver portfolio for high…
32Gbps Pseudo Random Bit Sequence Generator/Checker
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps.
Accelerates AI and Hyperscale Data Center Applications The 112G Ultra-Long-Reach (ULR) SerDes PHY delivers exceptional long-reach…
USB 2.0 femtoPHY in TSMC (16nm, N7) for Automotive
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
eUSB 2.0 PHY in TSMC (N5, N4P, N3E, N3P)
Synopsys provides designers with silicon-proven, configurable eUSB2 PHYs that are compliant with the USB-Implementers Forum (USB-…
10Gbps Multi-Link and Multi-Protocol PHY IP
Designed for multi-protocols running on single PHY macro and is compliant with USB 3.1, PCI Express (PCIe) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, QSGMII
028TSMC_LVDS_01 is a library including: Transmitter LVDS driver (TX_LVDS); Receiver LVDS driver (RX_LVDS); Reduced range link rec…
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 55LP
Full support for the JESD204B synchronous serial interface, compliant with the JESD204B.01 version specification, is provided via…