Camera Receiver - 5.0Gbps 8-Lane - TSMC 12FFC, 6FFC

The CL12812M8RIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP. The CL12812M8RIP5000 is designed to support data rate in excess of maximum 5Gbps utilizing SLVS-EC ver.3.0 BG3 interface specification.

This IP is expandable to 8, 16, 24 or more lanes.

Porting is also possible for processes other than the target process.

We can provide the original LINK controller (soft macro) that can be used with this PHY.

• SLVS-EC ver.3.0 BG3 compliant
• Supporting for Differential Input Signals
  • SLVS-EC (Maximum 5.0Gbps)
• Xtal Input Clock Frequency Selectable
  • 25MHz /50MHz /75MHz /37.125MHz /54MHz /24MHz /48MHz /72MHz
• Maximum Output Clock Frequency
  • 5Gbps 250MHz@ Select parallel data bus width to 20bit
• Power Supply: Vcc=1.8V (IO and Analog)
  • The core voltage is determined by the process node.(Inside Core)
• Maximum Lane Number: 24-Lane (8-Lane, 16-Lane also available)
  • 20-bit/Lane Parallel Outputs (SLVS-EC)
  • Including Power Down Mode

• This IP is supported almost CMOS Image Sensor. Thus if when the customer want to use customer's LSI other system set, the customer don't need to change IP, because this IP can change Interface type to same PAD for changing mode pin.
• The system customer can select from many CMOS image sensor for using out IP.
• We are updating CMOS Image Sensor model number of verify operation for getting information from customer and ourselves at all time.
• If the customer need combo Link-layer, we can provide them and can support system.
• We are provided CIS and TX Verilog Model. Thus the customer can confirm function by verilog simulation status.
• This IP can be implemented in 8-lane units and can be tailored to meet customer specifications.

• Camera Application
• Security Camera
• Mobile-Phone Camera
• DSC(Digital Still Camera)
• Medical Camera
• SLR
• 3D Camera
• Camcorder
• ISP(Image Signal Processor)

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Combo Link Layer IP(CD12812IP) and FPGA Board(Option)