USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
- USB 2.0
- TSMC
- 40nm
- LP eFlash
- Available on request
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
USB 2.0 nanoPHY in TSMC (65nm, 55nm, 40nm)
The Synopsys USB 2.0 nanoPHY provides designers with a Physical Layer (PHY) IP solution, designed for low-power mobile and consum…
USB 2.0 femtoPHY in TSMC (40nm, 28nm, 22nm, 16nm, 12nm, 10nm, N7, N6, N5, N3P)
The Synopsys IP USB 2.0 femtoPHY provides designers with a physical (PHY) layer IP solution for low-power mobile and consumer app…
Our SerDes architecture is in production in processes ranging from 12nm to 180nm and at rates from 100Mbps to 32.75Gbps and prove…
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in TSMC 28HPC+
The combination PHY comprises of a Serial ATA (SATA) compliant with the SATA 3.0 Specification, a Peripheral Component Interconne…
HDMI - Display Port Combo PHY IP, Silicon Proven in TSMC 28HPC+
The DisPlay Port/HDMI/DVI Receiver is a high performance combo PHY with Display Port Receiver and HDMI Receiver.
2 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_10 is LVDS receiver with rail to rail input range.
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins …
1 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_08 is LVDS receiver with rail to rail input range.
065TSMC_LVDS_07 is LVDS transmitter.
Programmable CMOS LVDS Transmitter/Receiver
LVDS device consists of one common bandgap reference voltage generator, a number of LVDS transmitter pad groups with their bias b…
TRC3114 is a Quad SerDes used as four independent 3.125Gb/s FC, BP, or cable transceiver or 10Gbps XAUI Transceive.
32Gbps SerDes IP in TSMC 12nm FFC
The relentless demand for higher data throughput in data centers and high-performance computing (HPC) systems drives the need for…
32Gbps SerDes IP in TSMC 22nm ULP
The relentless demand for higher data throughput in data centers and high-performance computing (HPC) systems drives the need for…
TSMC CLN5FF GUCIe LP Die-to-Die PHY
IGAD2DY11A is an LP (Low Power) Die-to-Die (D2D) PHY for SoIC-X Face-to-Face package.
USB-C 3.1/DP TX PHY for TSMC 6FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB 3.1 DisplayPort PHY - TSMC 10FF, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
32Gbps, 31 order, Pseudo Random Bit Sequence Generator / Checker
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps.
USB 2.0 PHY IP, Silicon Proven in TSMC 16FFC
The entire physical layer (PHY) IP solution for USB 2.0 was created to provide exceptional performance and consume little power.
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 55 ULP
The most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4.1 Specification, UniPro v1.8 Specific…
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 40 LP
The MIPI M-PHY Gear 4 IP is compatible with the most recent MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-…