Vendor: T2M GmbH Category: Single-Protocol PHY

JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 55LP

Full support for the JESD204B synchronous serial interface, compliant with the JESD204B.01 version specification, is provided via…

TSMC 55nm LP In Production View all specifications

Overview

Full support for the JESD204B synchronous serial interface, compliant with the JESD204B.01 version specification, is provided via the JESD204B Tx-Rx PHY IP interface. It offers a straightforward user interface to a variety of low-cost devices due to its interoperability. The JESD204B PHY is a fully functional transceiver with solo Tx and Rx capabilities.

Key features

  • Multiple lanes transceiver with data rate from 1Gbps to 16Gbps: Transceiver version including both receiver and transmitter
  • Transmitter only version available
  • 40bit/32bit/20bit/16bit selectable parallel data bus Independent per-lane power down control
  • Programmable transmit amplitude
  • Programmable 3-tap feed forward equalizer (FFE)
  • Embedded receiver equalization (CTLE and DFE) to compensate insertion loss
  • Build in self-test with multiple pattern generation and checker for production test
  • Flexible reference clock frequency range
  • Integrated LC-tank PLL and Ring OSC PLL
  • Integrated on-chip differential 100-ohm termination for reference clock
  • Low capacitance ESD structures
  • Integrated on-chip differential 100 ohm termination in TX and RX: Termination resistance auto calibration function (optional)
  • Support both Flip Chip Package and Wire Bonding Package
  • Testability: High Testability
  • Built-in pattern generator and checker including PRBS Internal serial loopback
  • Reliability: Lifetime: 10 years
  • Lifetime Average Temperature: up to 110 degC (include hot-spot)
  • Availability: 100%
  • ESD (HBM): over 2000V
  • ESD (CDM): over 250V
  • Latch-up: Satisfy JESD78 ClassII (Tj=125c), >100mA
  • Silicon Proven in TSMC 55nm LP

Benefits

  • Low Power Consumption
  • Low Physical Area compared to market standard
  • Operating Temperature: ~ 110degrees
  • Layered and Structured architecture

What’s Included?

  • Application Note / User Manual
  • Behavior model, and protected RTL codes
  • Protected Post layout netlist and Standard
  • Delay Format (SDF)
  • Frame view (LEF)
  • Metal GDS (GDSII)
  • Test patterns and Test Documentation

Silicon Options

Foundry Node Process Maturity
TSMC 55nm LP In Production

Specifications

Identity

Part Number
JESD204B Tx-Rx PHY IP in 55LP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Single-Protocol PHY IP core

Frequently asked questions about Single-Protocol PHY IP

What is JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 55LP?

JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 55LP is a Single-Protocol PHY IP core from T2M GmbH listed on Semi IP Hub. It is listed with support for tsmc In Production.

How should engineers evaluate this Single-Protocol PHY?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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