Complete PHY solution that is fully compliant to MIPI D-PHY specification version 1.2
- PHY
- MIPI D-PHY
- TSMC
- 130nm
- BCD+
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
Complete PHY solution that is fully compliant to MIPI D-PHY specification version 1.2
USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
Quad 3.125/6.25 Gbps Backplane SerDes
IP
Dual Parallel to Serial ATA 1.5/3.0Gb/s PHY Core
TRC3002CSA is a Dual Serial ATA (SATA) PHY core for interfacing serial data between Storage Device and external 2-port PHY.
PHY IO for PSRAM memory PHY, 1066Mbps on TSMC 22nm
The PHYIOs is used to transfer the Command/Address/Clk and Data between the memory controller PHY and the PSRAM device.
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
USB1.1 FS/LS PHY, TSMC 55ULP_EF
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
USB1.1 FS/LS PHY, TSMC 40ULP_EF
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
<4Gbps Low Power D2D Interface in TSMC 16nm & 28nm
A
Low Power D2D Interface in TSMC 16nm FFC/FFC+
A 600MBps Low Power Die-to-Die Interface in TSMC 16nm FFC/FFC+.
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices.
10/100/1000 base T ethernet Phy
IP
SerDes PHY IP in TSMC (7nm, 12/16nm, 22nm, 28nm)
M31 Serdes PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications.
10/100 Ethernet PHY for TSMC 22nm ULP
10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver.
USB3.0/PCIe2.0 Combo PHY in TSMC28HPC+
USB3PCIE20T28HPCP is a USB3.0 and PCIe 2.0 Combo PHY IP solutoin designed for a mobile and data consumer applications in T28nm pr…