Low Power D2D Interface in TSMC 16nm FFC/FFC+

This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.

As semiconductor designs continue to diversify, many successful products are not chasing the most advanced process nodes. Instead, they prioritize power efficiency, reliability, and long-term availability.

Integrated circuits are commonly tested for ESD robustness with 2 tests, Human Body Model (HBM) and Charged Device Model (CDM). Most engineers quickly grasp the procedure for HBM, but the CDM test is often poorly understood. This is unfortunate, because a large fraction of the ESD failures experienced in modern board assembly operations are CDM type failures. This article will describe the events which occur during a CDM test conducted using the widely accepted field induced CDM (FCDM) test.

Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.

As a member of the TSMC IP Alliance, Certus delivers production-proven IP that ensures seamless integration with TSMC process nodes, ranging from 180nm to 12nm.

In today’s data-driven world, high-speed, low-power communication is essential. Certus Semiconductor’s LVDS Transceiver delivers exactly that—optimized for GlobalFoundries’ 12nm CMOS process, it provides reliable, high-performance Low-Voltage Differential Signaling (LVDS) for next-generation designs.