Vendor: Certus Semiconductor Category: Custom

<4Gbps Low Power D2D Interface in TSMC 16nm & 28nm

A

Overview

A <4Gbps, Wide I/O Compatible, Die to Die Interface in TSMC 16nm and 28nm.

This silicon proven die to die interface includes IP in both TSMC 16nm FFC/FFC+ and 28nm HPM/HPC/HPC+. The I/O cells for both versions of the library are defined as TX only and RX only. The cells have two modes of operation: standard full rail to rail swing or a custom low noise psuedo-differential interface. The RX cells have a weak pull-down feature. The library is designed for Flip-chip/Die to Die packaging only, with no Wirebond option. Both library options have a common power bus architecture that when the cells are abutted, will feed through. There are no Power or Ground Pad/Cells, however all VDD and VSS connections will be made to the Core domain in upper metals. Both library options are ultra-low power, have a small footprint, MCM compliant, and have HBM & CDM robustness.

Operating Conditions for 16nm

Parameter Value
VDDIO 0.8V
I/O Device 1.8V
Core Use SVT Only
Cell Size 50x28.06um
BEOL M8 & below
VDD Core 0.8V +/- 10%
Temperature -40C to 125C
Operational Bit Rate 2Gbps1

Operating Conditions for 28nm

Parameter Value
VDDIO 0.9V
I/O Device 1.8V
Core Use SVT Only
Cell Size 50x25um
BEOL M8 & below
VDD Core 0.9V +/- 10%
Temperature -40C to 125C
Operational Bit Rate 2Gbps1

 Cells for 16nm D2D

Cell Name Width Description
UF_TX 50x25um TX Cell
UF_RX 50x25um RX Cell

Cells for 28nm D2D

Cell Name Width Description
UD_TX 50x30.5um TX Cell
UD_RX 50x30.5um RX Cell

Block Diagram

Silicon Options

Foundry Node Process Maturity
TSMC 28nm 28nm 280 nm

Specifications

Identity

Part Number
UF16_UD28
Vendor
Certus Semiconductor
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: United States

Learn more about Custom IP core

One Platform, Five Libraries: Certus Semiconductor’s I/O IP Portfolio for Every Application on TSMC 22nm ULL/ULP Technologies

Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.

Enabling RISC-V Vector Code Generation in MLIR through Custom xDSL Lowerings

The growing adoption of RISC-V in high-performance and scientific computing has increased the need for performance-portable code targeting the RISC-V Vector (RVV) extension. However, current compiler infrastructures provide limited end-to-end support for generating optimized RVV code from high-level representations to low-level implementations. In particular, existing MLIR distributions lack practical lowering paths that map high-level abstractions to RVV intrinsics, limiting their applicability for production-ready RISC-V kernels. This paper presents a compilation approach that combines MLIR with xDSL to bridge the missing lowering stages required for RVV code generation.

Frequently asked questions about Custom Die-to-Die IP cores

What is ?

is a Custom IP core from Certus Semiconductor listed on Semi IP Hub. It is listed with support for tsmc.

How should engineers evaluate this Custom?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Custom IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP