JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…
- TSMC
- 55nm
- GP
- In Production
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
JESD204B Tx-Rx PHY IP, Silicon Proven in TSMC 65GP/55GP
The JESD 204B controller IP is optimized and silicon agnostic implementation of the JEDEC JESD204B standard targeting any ASIC, F…
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
TSMC CLN7FF GLink-3D Die-to-Die Slave PHY
IGAD2DX03A is a GLink-3D high speed die-to-die interface Slave PHY.
TSMC CLN5FF GLink-3D Die-to-Die Master PHY
IGAD2DY02A is a GLink-3D high speed die-to-die interface Master PHY.
TSMC CLN5FF GLink 2.0 Die-to-Die PHY
IGPD2DY01A is a high-speed Die-to-Die interface PHY that transmits data through TSMC packaging solutions: Integrated Fan-Out (InF…
TSMC CLN5FF GLink 2.3LL Die-to-Die PHY
IGAD2DY04A is a high-speed die-to-die interface PHY which transmits data through TSMC packaging solutions: Integrated Fan-Out (In…
MIPI D-PHY Transmitter/Receiver for TSMC 22nm ULL
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 22nm ULL process.
MIPI D-PHY Transmitter/Receiver for TSMC 40nm LP
The MIPI® D-PHY Transmitter/Receiver is useful 2 Data Lanes transmitter/receiver hard macro for DSISM/CSI-2® of TSMC 40nm LP process.
The T180BCDLVDSV1 IP is a mini-LVDS TX and RX PHY based on TSMC 180nm BCD process.
The T40LP_MIPIDPHYV01 IP is a MIPI D-PHY and LVDS based on TSMC 40nm LP process.
The IP is a USB PHY based on TSMC 180nm process.
TSMC CLN6FF/7FF Die-to-Die Interface PHY
This IGAD2DX01A test report shows the functional and characterization test result of GUC Die-to-Die Interface PHY IP for 8 Gbps o…
ONFI 4.1 PHY IP (Silicon Proven in TSMC 12FFC)
ONFI PHY block is used to either transmit signal and data to NAND Flash interface or receive the data from NAND Flash by Flash co…
Special I/O-eMMC/SDIO in TSMC(22nm, 28nm, and 40nm)
SD (Secureity Digital) and eMMC (embedded MultiMedia Card) I/Os are non-volatile memory interface technologiesy with high bandwid…
PCIe 4.0 PHY in TSMC(6nm,7nm, 12nm,16nm)
M31 PCIe 4.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
ONFI I/O 6.0/5.1/5.0 IP in TSMC(3nm, 5nm, 6nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm)
ONFI I/O is a non-volatile memory interface technology with high bandwidth capabilities, mainly developed for flash storage appli…
The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…
The CI Plus library provides a programmable bi-directional I/O cell designed to meet the signal interface requirements of the Com…
USB BCK Technology in TSMC (22nm, 40nm, 55nm, 65nm, 110nm)
In USB product series, M31 not only provides customers with a standard USB PHY solution, but also offers a unique BCK(Built-in Cl…
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.