Bridging the MACsec Gap: Add Line-Rate Security Without Redesigning Your Ethernet Subsystem
Now place a MACsec engine between an existing MAC and PHY with new xMII bridges; handle key management with new MKA stack and drivers
Vendor:
Sunplus Technology Co., Ltd.
Category:
Ethernet
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver.
Overview
SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active
circuitry required to convert data stream to and from a Media Access Control (MAC) and from and to the
physical media. It supports 100Base-TX and 10BASE-T networks over twisted-pair cable in full-duplex or half-duplex mode. Both the Media Independent Interface(MII)
and Reduced Media Independent Interface (RMII) are supported.
circuitry required to convert data stream to and from a Media Access Control (MAC) and from and to the
physical media. It supports 100Base-TX and 10BASE-T networks over twisted-pair cable in full-duplex or half-duplex mode. Both the Media Independent Interface(MII)
and Reduced Media Independent Interface (RMII) are supported.
Key features
- TSMC 12nm CMOS Logic FinFET Compact
- Power Supply: 0.8V, 1.8V and 3.3V
- Metal Stack Option:1P8M (2xa1xd3xe vhv 1z) with RDL
- Operating Temperature: -40oC~125oC
- Fully IEEE 802.3 10/100 Base-TX compliant and supports EEE
- Integrated MDI termination resistors
- Supports MII and RMII interfaces
- Design for Testability with extensive testability feature and 95% fault coverage
- Programmable loopback mode for diagnostic
- Supports programmable LED output for different applications and power on LED Self-Test
- Supports 24M/25M/27M/50M REFCLK clock sources
- Supports WOL (Wake-On-Lan) functionality
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| TSMC | 12nm | FFC | — |
Specifications
Identity
Part Number
SP-10_100_ETHERNET-T12FFC
Vendor
Sunplus Technology Co., Ltd.
Type
Silicon IP
Provider
HQ:
Taiwan 30076
Learn more about Ethernet IP core
Single Pair Ethernet and TSN: The In-Robot Network Behind the Next Humanoid Robots
Humanoid robots are moving from research demos toward real products, and the network inside them is becoming the hard problem. Single Pair Ethernet and Time-Sensitive Networking are emerging as the answer, and CAST already builds the IP cores that make it deterministic.
SerDes, Ethernet and the silicon that connects them: Why SerDes for high-bandwidth sensors?
The evolution to centralized vehicle computing is driving new connectivity requirements. Discover how SerDes supports high-speed sensor data streaming while reducing system complexity.
Scale-Up Ethernet Ecosystem Ramps Up: Cadence ESUN Controller IP Available
Building on its High-Speed Ethernet controller IP family, Cadence provides ESUN-ready controller IP for next-generation AI scale-up networking.
Why 10BASE-T1S Automotive Ethernet SoC Verification Needs More Than Simulation?
This blog post explores how the team verified a 10BASE-T1S automotive ethernet subsystem using a Cadence tools-based multi-platform verification, which unifies simulation, emulation, and formal verification techniques.
Enabling the Next Generation of AI Infrastructure with Ethernet for Scale-Up Networking (ESUN)
Learn how ESUN enhances Ethernet for lossless, predictable AI scale-up networking—cutting overhead, reducing tail latency, and improving efficiency.
Frequently asked questions about Ethernet IP cores
What is Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC?
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC is a Ethernet IP core from Sunplus Technology Co., Ltd. listed on Semi IP Hub. It is listed with support for tsmc.
How should engineers evaluate this Ethernet?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Ethernet IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.