CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard.
- Channel Coding
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard.
Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requireme…
The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
64-bit RISC-V Application Processor Core
The A70 is a 64-bit RISC-V application processor aimed at systems running Linux.
64-bit RISC-V Application Processor Core
The A70 is a 64-bit RISC-V application processor aimed at systems running Linux.
Multi-Channel Signature Calculator
IP
Analog TV Demodulator and Decoder IP (Silicon Proven)
The Analog TV Demodulator and Decoder IP core is extracted from a production chip and a silicon-proven IP core.
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructi…
64-Bit 8-stage superscalar RISC-V processor
The 64-bit NX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instruct…
DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…
DVB-S2X WideBand Demodulator IP
This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integra…
DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven)
This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integra…
AHB Secure Subsystem - ARM Cortex M3
The Secure AHB Performance Subsystem is a high-performance AHB subsystem that allows for a high level of hardware and software se…
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or…
The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm.
2K TicoRAW Encoder / Decoder for RAW CFA sensor data compression
Engineered at intoPIX, TicoRAW is an , lossless quality, low-power, low-memory and line-based image processing and compression te…
8K TicoRAW Encoder / Decoder for RAW CFA sensor data compression
Engineered at intoPIX, TicoRAW is an , lossless quality, low-power, low-memory and line-based image processing and compression te…
4K TicoRAW Encoder / Decoder for RAW CFA sensor data compression
Engineered at intoPIX, TicoRAW is an , lossless quality, low-power, low-memory and line-based image processing and compression te…
Our Processor for high embedded performance with RISC-V instruction-set compatibility, permit users to grasp the rich ecosystem o…
The AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel.