Vendor: T2M GmbH Category: Channel Coding

DVB-S2-LDPC-BCH IP

The DVB-S2-LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.

Overview

The DVB-S2-LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on inner LDPC (Low-Density Parity Check) codes concatenated with outer BCH (Bose ChaudhuriHocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.

Key features

  • Irregular parity check matrix
  • Layered Decoding
  • Minimum sum algorithm
  • Soft decision decoding
  • BCH decoder works on GF (2m) where m=16 or 14 and corrects up to t errors, where t = 8, 10 or 12
  • ETSI EN 302 307-1 V1.4.1 (2014-11) compliant
  • Long and short frame lengths
  • No error floor to QEF in Standard
  • Easy to integrate within receiver all code rates and modulation orders

Block Diagram

DVB-S2-LDPC-BCH IP block diagram

Benefits

  • High performance
  • High data rate

Applications

  • DVB-S2

What’s Included?

  • Synthesizable Verilog
  • System Model (Matlab)
  • Verilog Test Benches Documentation

Specifications

Identity

Part Number
DVB-S2-LDPC-BCH IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

Learn more about Channel Coding IP core

Frequently asked questions about Channel Coding IP cores

What is DVB-S2-LDPC-BCH IP?

DVB-S2-LDPC-BCH IP is a Channel Coding IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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