High Speed Data Recorder
A new IP Core from ASICS World Services, provides a complete high speed data recorder, in one easy to use block.
Vendor:
ASICS World Services, LTD.
Category:
Data Compression
ZLIB compatible compression and decompession, with DMA and AXi interface
This is a high performance, small footprint ZLIB compatible IP Core.
Overview
This is a high performance, small footprint ZLIB compatible IP Core. It features 3 DMA engines, AXI interconnect and separate clocks for AXI interfaces and compression/decompression engines.
ARCHITECTURE
Separate DMA engines for Scatter/Gather descriptors and data movement, alow non stop processing of data.
Key features
- 100% ZLIB compatible
- Fixed Huffman encoding
- Subset of LZ77
- Scatter/Gather DMA engine
- Utilizes linked list of transfer descriptors
- Compression and Decompression in one IP Core
- Configurable Data Path to 32, 64 or 128 bit
- Fully AXI-4 compatible
- AXI-Light for register Interface
- Separate clocks for engines and AXI interface
Block Diagram
ZLIB_1 block diagram
Benefits
- High Performance
- small footprint
Applications
- any
What’s Included?
- Verilog Source Code
- Test Bench
- Documentation
- Tech Support
Specifications
Identity
Part Number
ZLIB_1
Vendor
ASICS World Services, LTD.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
Learn more about Data Compression IP core
SATA Connectivity solutions for Xilinx FPGAs
This Whitepaper gives an overview over the Serial ATA (SATA) protocol and the implications when integrating SATA into an FPGA-based programmable system. Besides details of the different protocol layers, we will discuss the hardware and software components for building a complete, reliable, high-performance SATA solution by utilizing a design platform from Missing Link Electronics (MLE).
Frequently asked questions about Data Compression IP
What is ZLIB compatible compression and decompession, with DMA and AXi interface?
ZLIB compatible compression and decompession, with DMA and AXi interface is a Data Compression IP core from ASICS World Services, LTD. listed on Semi IP Hub.
How should engineers evaluate this Data Compression?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Data Compression IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.