These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either S…
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Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either S…
CCSDS AR4JA LDPC Encoder & Decoder
The CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard.
RISC-V processor - 32 bit, 5-stage pipeline
The L50(F) is a medium-sized, efficient 32-bit embedded RISC-V processor aimed at embedded systems with mid-range processing requ…
DisplayPort 1.4 FEC Receiver (Rx)
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified …
Fully Configurable LDPC Encoder
In channel coding redundancy is inserted in the transmitted information bit-stream.
Programmable OFDM Channel Estimator
The wideband OFDM signal suffers from frequency selective fading.
The DVB-S2X modulator is a low-complexity high-performance solution that allows for symbol rates of up to 250 MSymb/s (2 Gbit/s f…
PMCC_XCM_64x64_D IP block is a low-power array of 1GHz clocked Cross-Correlator cells that are synchronously acquiring two sets o…
Cross-Correlator With 64x2 Channels
PMCC_XCM_64x64 is an IP block capable of calculating the cross-correlations between 64x2 analog signals supplied to the inputs AR…
DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the additio…
Chroma Re-sampler core can be used as chroma sub sampling or chroma up sampling.
The 80188EB is a 16-bit microprocessor core, executes instruction list compatible with 80188EB microprocessor.
The 80188XL is a 16-bit microprocessor core, executes instruction list compatible with 80188XL microprocessor.
The 80186XL is a 16-bit microprocessor core, executes instruction list compatible with 80186XL microprocessor.
The 80186EC is a 16-bit microprocessor core, executes instruction list compatible with 80186EC microprocessor.
LTE and LTE (LTE-A) are the mobile broadband standard of the 4th generation.
AHB Performance Subsystem - ARM Cortex M3
The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs n…
AHB Low Power Subsystem - ARM Cortex M0
The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SO…
Single precision fixed-size streaming floating-point FFT
This FFT circuit employs unique architectural characteristics providing functionality and capabilities not possible with other FF…
CCSDS LDPC Encoder and Decoder
The CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard.