Vendor: T2M GmbH Category: Channel Coding

DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)

The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…

Overview

The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single output interface. The data coming from the 8 demodulators are multiplexed and decoded by the same engine. After decoding, 8 packet delineators do the demultiplexing and DVB-S2 de-framing before sending data to the output transport stream manager.

For a 258-MHz clock we may have a maximum data rate of 258 Mchannel-bit/s (megaLLRs)at the input to the FEC decoder. Advanced power-saving features have been implemented, the LDPC stops once the solution is sufficiently converged and the various blocks of the IC (tuner, demodulator, LDPC, Legacy FEC, and so on) may be completely shut down if not required. The device also supports Wake-on-network PID.

Key features

  • Multiplexed LDPC/BCH decoder: The DVB-S2 FEC block can simultaneously decode 8 independent input streams. Each input stream has its own input connection. However, the cell only includes one LDPC decoder and one BCH decoder. Thus, the 8 input streams are stored in 8 independent buffers. When a frame is ready, it is processed in the LDPC decoder, then in the BCHdecoder and finally output to the appropriate transport stream.
  • LDPC decoder: The LDPC decoder can decode normal and short frames and all DVB-S2 and S2X Broadcast and Interactive profiles, but not VLSNR.
  • BCH Decoder: The BCH decoder is able to correct up to 12bits for Code rates where more than 192 redundancy bits are available. As such, correction is only possible up to 10bits for 2/3 and 5/6 code rates, and only up to 8bits for 8/9 and 9/10 code rates.
  • Packet Delinter: The packet delineator is used for descrambling, checking the integrity of BBFrame headers, processing the cache and data fields and providing a lock indicator

Benefits

  • Ready to License
  • Silicon Proven , Extratced from Production Chips

Applications

  • Consumer Satellite broadband gateway.
  • Professional Satellite demodulator
  • component.
  • Multi-dwelling unit.
  • IP-LNB.
  • Satellite multi-room server.
  • Multi-channel Satellite STB and PVR.

What’s Included?

  • Verilog Source RTL Code plus Simulation Environment
  • RTL/C Source Code
  • Physical Design scripts - Synopsys synthesis
  • Hardware simulation test bench with regression test suit
  • Reference platform drivers
  • Complete Design Database

Specifications

Identity

Part Number
DVB-S2X Decoder IP
Vendor
T2M GmbH
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

T2M GmbH
HQ: Germany

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Frequently asked questions about Channel Coding IP cores

What is DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)?

DVB-S2X LDPC/BCH Decoder IP (Silicon Proven) is a Channel Coding IP core from T2M GmbH listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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