Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
3.5 to 5 GHz, 7 to 10 GHz and 14 to 20 GHz FMCW Modulator for RADAR
The WEA520SFMCW22G is an ultra-fast ultra-linear FMCW frequency synthesizer capable of generating 1400 MHz Chirps at 20 GHz frequ…
IEEE 802.11 n/ac/ax LDPC Decoder
The Low Density Parity Check (LDPC) codes are , capacity approaching channel codes and have exceptional error correction capabili…
IEEE 802.11 n/ac/ax LDPC Encoder
The Low Density Parity Check (LDPC) codes are , capacity approaching channel codes and have exceptional error correction capabili…
DVB-RCS2 Multi-Carrier Receiver
DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second…
IP cores for ultra-low power AI-enabled devices
Each nearbAI core is an ultra-low power neural processing unit (NPU) and comes with an optimizer / neural network compiler.
High performance dual-issue, out-of-order, 7-stage pipeline superscalar core
RiVAI-R1 is a dual-issue, Out-of-Order execution, 7-stage pipeline, 32-bit RISC-V CPU core IP that supports the RV32IMFAC instruc…
High performance dual-issue, out-of-order, 7-stage Vector processor (DSP) IP
World's first audio DSP IP with RISC-V Vector processor architecture RiVAI-V1 is a dual-issue, Out-of-Order execution, 7-stage pi…
32 Bit - Embedded RISC-V Processor Core
The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requireme…
32 bit - Compact RISC-V Processor Core
The L11 is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements.
4-/8-bit mixed-precision NPU IP
Features a optimized network model compiler that reduces DRAM traffic from intermediate activation data by grouped layer partitio…
This is an LDPC decoder compliant with the IEEE 802.11 n/ac/ax standards.
IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications.
DVB-S2 LDPC BCH Decoder and Encoder
The DVB-S2 LDPC-BCH block is a FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite.
The DVB-S2X LDPC Decoder is a FEC core decoder for Digital Video Broadcasting via Satellite.
Low Power AI Micro-Core IP generated with a fully customizable and flexible core generator.
3GPP compliant coding and modulation for Physical Shared Channels The Physical Uplink Shared Channel (PUSCH) is used to for uplin…
Ultra low power inference engine
Innatera's ultra-efficient neuromorphic processors mimic the brain's mechanisms for processing sensory data.
DVB-C Demodulator IP (Silicon Proven)
The DVB-C Demodulator IP core is a silicon-proven IP core and extracted from the production chip, It is a QAM (quadrature amplitu…
DVB-T2/T Demodulator and Decoder IP (Silicon Proven)
The DVB-T2/T IP is a silicon-proven IP core extracted from a production chip contains FEC.
ZLIB compatible compression and decompession, with DMA and AXi interface
This is a high performance, small footprint ZLIB compatible IP Core.