Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
CPU
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructi…
Overview
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compression instructions, “P” Packed-SIMD/DSP (draft) instructions, “B” bit manipulation, and Andes performance enhancements, plus Andes Custom Extension™ (ACE) for user-defined instructions. It features MMU for Linux based applications, dynamic branch prediction for efficient branch execution, dual-issue of common instruction pairs, instruction and data caches and local memories for low-latency accesses. A45 equipped with comprehensive SIMD/DSP instructions that can boost the performance of voice, audio, image and signal processing. Its ”B” extensions provide some combination of code size reduction, performance improvement, and energy reduction, and “FD” extensions support IEEE754-compliance single and double precision floating point instructions. A45 incorporates MemBoost to enhance memory bandwidth and reduce memory latencies for intensive memory accesses. Other features include ECC for memory soft error protection, Platform-Level Interrupt Controller (PLIC) with enhancements for vectored dispatch and priority-based preemption, CoDense™ and StackSafe™ for software quality improvement, PowerBrake and WFI for power management.
Key features
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant to RISC-V RV32 GCBP little endian:
- RV-GC: Integer, single/double precision floating point and 16-bit extensions
- RV-B Bit manipulation extensions
- RV-P (draft) DSP/SIMD extensions
- Andes V5 performance/code size extensions
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch prediction to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
- Memory Management Unit (MMU), Physical Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
- MemBoost for heavy memory transactions
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
Block Diagram
A45 block diagram
Benefits
- Performance
- 32-bit in-order dual-issue 8-stage pipeline CPU architecture
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- DSP/SIMD extensions
- Floating point extensions
- Andes extensions, architected for performance and functionality enhancements
- 16/32-bit mixable instruction format for compacting code density
- Advanced low power branch predication to speed up control code
- Return Address Stack (RAS) to accelerate procedure returns
- Memory Management Unit (MMU), Physical
- Memory Protection(PMP), and programmable Physical Memory Attribute (PMA)
- MemBoost for heavy memory transactions
- Flexibly configurable Platform-Level Interrupt Controller (PLIC) for supporting wide range of system event scenarios
- Enhancement of vectored interrupt handling for real-time performance
- Advanced CoDense™ technology to reduce program code size
- Flexibility
- Easy arrangement of preemptive interrupts
- StackSafe™ hardware to help measuring stack size, and detecting runtime overflow/underflow
- ECC or Parity check on level-one memories for fault protection
- Several configurations to tradeoff between core size and performance requirements
- Power Management
- PowerBrake, QuickNap™ and WFI (Wait For Interrupt) for power management at different occasions
Applications
- Linux Operating System Based Applications
- Networking and Communications
- ADAS/IVI/V2X
- Video and Image Processing
- Machine/Deep Learning acceleration
- Advanced Storage Device Control
What’s Included?
- AndesCore™ A45 Single-core Processor with AE350 AXI Platform
- Pre-integrated A45 single-core CPU subsystem, PLIC, Debug Module, and AXI Platform
Specifications
Identity
Part Number
A45
Vendor
Andes Technology Corp.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
Learn more about CPU IP core
Adding RISC-V CPU Custom Extensions Can Boost Performance, Reduce Power, and Cut Cost in 5G, AI. AR/VR, and IoT applications
By Andes
Building security into an AI SoC using CPU features with extensions
With the rapid deployment of artificial intelligence (AI), the focus of AI system on chip (SoC) design has been on building smarter, faster and cheaper
When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives
I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also RISC-V’s biggest tailwind yet.
AndeSentry – Andes’ Security Platform
Security has become a critical requirement across a wide range of applications, including mobile devices, automotive infotainment systems, and embedded platforms such as robotics. These systems must deliver robust security functionality with minimal performance overhead, which in turn requires tight and seamless integration between hardware and software to achieve optimal efficiency.
How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
Unlike fixed-ISA alternatives, RISC-V enables developers to create domain-specific processors for their systems-on-chip (SoCs). Custom instructions can boost throughput, reduce energy consumption, and shrink silicon area, all while preserving software compatibility and ecosystem portability. RISC-V’s open nature also reduces vendor lock-in, enabling faster innovation across automotive, AI, security, and high-performance computing (HPC).
Frequently asked questions about CPU IP cores
What is 32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux?
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.