Vendor: Codasip Category: CPU

Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers

The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requireme…

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Overview

The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requirements. The core has a 3-stage pipeline and has 32 general-purpose registers.
The core includes optional L1 data and instruction caches, optional instruction and data TCM, optional 8 or 16 PMP regions, an interrupt controller and RISC-V Debug module optionally with PC trace.
Like with all Codasip RISC-V cores, it is possible to create custom instructions using Codasip Studio to extend the L30 and to generate corresponding hardware and software development kits.
 

Key features

  • 32-bit RISC-V core
  • Available in two versions:
    • RV32IMC
    • RV32IMCF
  • 32 general purpose registers
  • Either parallel multiplier
  • 3-stage pipeline
  • Dynamic branch predictor
  • RISC-V privilege mode support:
    • Machine, User
  • Internal interrupt controller
    • Up to 256 sources
  • Optional FPU (L30F)
  • Optional instruction and data tightly coupled memories (TCM)
  • Optional 8 or 16 PMP regions
  • Optional L1 data and instruction caches
  • Standard RISC-V CLINT
    • Up to 256 sources
  • Wakeup interrupt controller
  • NMI
  • On-chip debugger
    • RISC-V Debug module
  • 2/4 pin JTAG
  • 2-8 breakpoints/watchpoints

Block Diagram

Codasip L30(F) block diagram

Benefits

  • Flexibility
    • Wide choice of configuration options.
  • Extensibility
    • Ability to create custom RISC-V extensions to optimise performance
    • Efficient architectural exploration of custom extensions with Studio
    • Automatic HDK and SDK generation from Studio
    • Rigorous verification of modified L30 core using UVM

Applications

  • The L30 is aimed at low- to mid-range embedded applications such as IoT, always on sensors, wireless connectivity, audio, motor control and display control.

What’s Included?

  • Human-readable and structured RTL in either:
    • Verilog
    • VHDL
    • System Verilog
  • Hardware development kit (HDK)
    • Synthesis scripts
    • Simulation testbenches
    • Debug support
  • Software development kit (SDK)
    • LLVM C-compiler
    • Assembler
    • Disassembler
    • Linker
    • Instruction-accurate simulator
    • Cycle-accurate simulator
    • Profiler
  • Option for extending L30
    • CodAL model for Codasip Studio

Specifications

Identity

Part Number
Codasip L30(F)
Vendor
Codasip
Type
Silicon IP

Compute

CPU Architecture
RISC-V

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Codasip
HQ: Germany
Contact Codasip

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Frequently asked questions about CPU IP cores

What is Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers?

Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers is a CPU IP core from Codasip listed on Semi IP Hub.

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