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Vendor:
IObundle, Lda
Category:
CPU
RISC-V-based SoC template
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or…
Overview
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or ASIC. It supports stand-alone and booting modes, and can use internal RAM or an external DDR controller via L1/L2 cache systems.
Key features
- Based on the picorv32 RISC-V CPU
- (Re)programmable via UART
- Runs from internal RAM or external AXI4 memory (DDR or other)
- L1 instruction and data caches
- UART
Block Diagram
IOb-SoC block diagram
Benefits
- With IOb-SoC you can quickly and inexpensively build a complex embedded SoC
- Very small size and power consumption
Applications
- All kinds of low-cost low-power embedded systems
What’s Included?
- This IP can be downloaded for free from https://github.com/IObundle/iob-soc
- Premium features/services available on-demand:
- Higher performance CPU
- Custom hardware accelerators
- Custom peripherals
- Custom software
Specifications
Identity
Part Number
IOb-SoC
Vendor
IObundle, Lda
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Portugal
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Frequently asked questions about CPU IP cores
What is RISC-V-based SoC template?
RISC-V-based SoC template is a CPU IP core from IObundle, Lda listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.