Ultra low power C-programmable DSP core
NXP conducts a successful licensing program for this embedded DSP core for ultra low power applications.
- DSP Core
- now
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
Ultra low power C-programmable DSP core
NXP conducts a successful licensing program for this embedded DSP core for ultra low power applications.
Dolby Digital/AC-3/MPEG Audio Decoding Core
The J1 is a core cell design of an application specific signal processor which performs both Dolby Digital/AC-3 and MPEG audio de…
High Speed CCSDS Turbo Decoder with Optional Viterbi Decoder
This is a CCSDS compatible 16 state error control turbo decoder.
The CMS0009 DVB-T/DVB-H Modulator provides all the necessary processing steps to modulate a single (or pair of hierarchical) tran…
IEEE 802.16 WirelessMAN OFDM Channel Codec
The CMS0005 802.16 Channel Codec provides all of the functionality necessary to implement the back end data processing in an 802.…
High Speed Inmarsat Compatible Turbo Decoder
This is an Inmarsat compatible 16 state error control turbo decoder.
The CMS0002 Viterbi Decoder core implements Viterbi’s algorithm for maximum likelihood decoding of non-feedback convolutional cod…
The CMS0010 DVB-S/-DSNG Modulator with integrated Reed-Solomon encoder has been designed specifically to address the requirements…
The Lempel-Ziv (LZ) compression methods are among the most popular algorithms for lossless data compression.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible 3GPP (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) error control decoder.
3GPP UMTS LTE 3GPP2 cdma2000 1xEV-DV 1xEV-DO 8 state turbo encoder
This is a high speed 8 state 3GPP™ (UMTS and LTE) and 3GPP2 cdma2000 (1xEV-DV Release D and 1xEV-DO Release B) compatible paralle…
Configurable transformer accelerator
For fast, low-power edge AI inference on Stories260K, Stories15M, SmolLM 135M, LLaMA 3.2, and custom models, supporting FP32, INT8, and INT4.
64-bit, RISC-V, ultra-high performance processors
The Akeana 5000 Series of processors is configurable and customizable, supporting applications such as mobile computation, data c…
64-bit, RISC-V, performance and data computation processors
The Akeana 1000 Series of processors is configurable and customizable, supporting applications from smart homes and wearables, to…
32-bit, RISC-V, deeply embedded processors
The Akeana 100 Series of processors is configurable and customizable, supporting applications from embedded microcontrollers to e…
32-bit RISC multiprocessor platform for the most demanding computational tasks
VisionNet v1.0 is a configurable CNN accelerator IP designed to deliver efficient edge inference for vision workloads.
Configurable CPU tailored precisely to your needs
The TES µEngine concept enables complex digital circuit tasks to be created as software-defined functions executed by mini-comput…
Enabling Next-Generation Voice AI and Immersive Audio Applications With the rise of immersive audio and AI in home entertainment,…
Parameterizable compact BCH codec
The core targets the lower-performance error correction applications using Bose–Chaudhuri–Hocquenghem codes (BCH codes) that prio…