Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
NPU
High performance-efficient deep learning accelerator for edge and end-point inference
AndesAIRE™ AnDLA™ I350 is a deep learning accelerator (DLA) designed to enable high performance-efficient and cost-sensitive AI s…
Overview
AndesAIRE™ AnDLA™ I350 is a deep learning accelerator (DLA) designed to enable high performance-efficient and cost-sensitive AI solutions for edge and end-point inference. It supports popular deep learning frameworks, such as TensorFlow Lite, PyTorch, and ONNX, and performs versatile neural network operations such as convolution, fully-connect, element-wise, activation, pooling, channel padding, upsample, concatenation, etc. in the int8 data type. It also features an internal Direct Memory Access (DMA) and local memory, utilizing the best computing power of the hardware engines. Operation fusion techniques are also adopted in the AnDLA™ I350 to perform most common operator sequences more efficiently. The key configurable parameters of AnDLA™ I350 include the MAC number from 32 to 4096, and SRAM size from 16KB to 4MB, and provide flexible computing power from 64 GOPS to 8 TOPS (at 1 GHz) for a wide range of applications.
Development Tools
- AndesAIRE™ NN SDK
- NNPilot™ neural network optimization tool suite
- TensorFlow Lite for Microcontrollers for AnDLA™
- AnDLA™ driver and runtime
- AndesAIRE™ NN Library
- AndeSight™ IDE
Key features
- Configurable MACs from 32 to 4096 (INT8)
- Maximum performance 8 TOPS at 1GHz
- Configurable local memory: 16KB to 4MB
- Multi-dimension DMA
- Four 64-bit AXI bus interfaces
- NN type: CNN inference
- NN models:
- Image and Video: AlexNet, VGG-16/19, MobileNet-v1/v2/v3, ResNet-8/50, Tiny YOLO v1/v2, YOLO v1/v2/v3/v4/v5, SSD MobileNet v1/v2, Inception v2, EfficientNet-lite, MobileFaceNet, BlazeNet
- Speech/Voice and audio: LSTM, RNN, GRU
- Operators: Conv2d, depthwise convolution, pointwise convolution, transpose convolution, dilated convolution, element-wise (add, sub, mul), fully-connected, activation (ReLU, leaky ReLU, sigmoid, Tanh, ReLU6, SiLU), pooling (max, ave), upsample, concatenation, batch normalization, channel padding
- Operator fusion
- NHWC data format
Block Diagram
AndesAIRE™ AnDLA™ I350 block diagram
Applications
- AIoT device / TinyML on edge and end-point
- Smart camera
- Smart sensor
- Sensor hub
- Wearable
- Smart home appliance
- Robotic
Specifications
Identity
Part Number
AndesAIRE™ AnDLA™ I350
Vendor
Andes Technology Corp.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
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Frequently asked questions about NPU IP cores
What is High performance-efficient deep learning accelerator for edge and end-point inference?
High performance-efficient deep learning accelerator for edge and end-point inference is a NPU IP core from Andes Technology Corp. listed on Semi IP Hub.
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Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this NPU IP.
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