CCSDS Rate 1/2 TC and TM LDPC Encoder
The LCE03C is a low complexity encoder for the CCSDS rate 1/2 telecommand (TC) and telemetry (TM) low density parity check (LDPC)…
- Channel Coding
- Now
- CCSDS 231.0-B-3 Blue Book S…
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
CCSDS Rate 1/2 TC and TM LDPC Encoder
The LCE03C is a low complexity encoder for the CCSDS rate 1/2 telecommand (TC) and telemetry (TM) low density parity check (LDPC)…
Power and area optimised Bitcoin miner engine
The eSi-BTC core is a Bitcoin miner engine that perform double SHA256 Hash.
The Rad Hard eFPGA IP cores leverage the proven Australis eFPGA generation flow to deliver customizable, radiation-tolerant solut…
The demand for high-speed data connection services develops in tandem with the number of internet users and multimedia apps.
multiple users and data streams must be processed concurrently in a contemporary communication system based on existing 4G and fu…
Quadrature Amplitude Modulation: Modulator and Demodulator
QAM Modulator and Demodulator combine two amplitude modulation signals into a single data transfer channel: 1.
Crest Factor Reduction IP Core
Crest Factor Reduction (CFR) is a technique for lowering a waveform’s power ratio from higher to average.
DVB-RCS2 Turbo Decoder and Encoder
On the transmitter side, the turbo-phi encoder architecture is based on a parallel concatenation of two double-binary Recursive S…
Digital Predistortion (DPD) IP Core
The next fifth-generation (5G) wireless networks promise connection speeds and data rates that are 100 times faster than current …
SCR6 is a high-performance, silicon-proven, 64-bit RISC-V processor core.
Highest performance four-issue, out-of-order RISC-V vector application processors
The latest generation SiFive Performance™ P600-Series processors are the highest performance commercially licensable RISC-V proce…
The Synopsys ARC® VPX DSP Family is optimized for the unique power, performance and area (PPA) requirements of embedded workloads…
Versatile, Ultra-Low-Power DSP for Audio, Voice, Vision, and AI
Smallest, ultra-low-energy DSP for always-on sensor fusion, always-listening voice trigger, and Bluetooth/BLE codecs The Cadence®…
Compact LossLess Encoder RTL Core
Extremely high throughput contributes to realization of the complete lossless compression and decompression.
1:2 Fixed Length Visually Lossless Compression/Decompression [RGB/YCbCr]
Fixed Length Visually Lossless Compression [RGB/YCbCr]
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer.
Tensilica AI Max - NNA 110 Single Core
Single-core neural network accelerator offering from 0.5 to 4 TOPS Optimized for machine learning inference applications The Cade…
The LDPC Error Correction Core (Alcyone) delivers industry- error correction performance to enable 2D/3D, SLC/MLC/TLC/QLC NAND Fl…
CCSDS turbo encoder with sync marker, pseudo randomiser and input memory
This is a high speed 16 state CCSDS compatible parallel concatenated turbo encoder with sync marker, optional pseudo-randomiser a…