DVB-C2 LDPC/ BCH Decoder
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
Overview
In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.
Key features
- Irregular Parity Check Matrix
- Layered Decoding
- Minimum Sum Algorithm
- Configurable Number of Iterations
- Soft Decision Decoding
- ETSI EN 301 769 V1.3.1 (2015-10) compliant
What’s Included?
- Synthesizable Verilog
- System Model (Matlab) and documentation
- Verilog Testbenches
- Documentation
- FPGA testing environment
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Channel Coding IP cores
What is DVB-C2 LDPC/ BCH Decoder?
DVB-C2 LDPC/ BCH Decoder is a Channel Coding IP core from Global IP Core Sales listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.