High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.
- Arithmetic Units
Compute and acceleration IP cores are specialized hardware blocks designed to improve performance and efficiency in modern SoC and ASIC designs.
This category covers a diverse ecosystem of processing technologies, including CPU and microcontroller cores for embedded control and software execution, AI/ML accelerators for neural network processing, DSP and math engines for real-time signal processing, data compression accelerators for efficient storage and communications, and eFPGA fabrics that provide post-silicon flexibility and hardware reconfigurability.
Whether you are designing for edge AI, automotive systems, consumer electronics, or data center acceleration, you can identify the right IP to optimize your system performance.
High-speed fully pipelined 32-bit floating-point adder/subtractor based on the IEEE 754 standard.
High-speed fully pipelined 32-bit floating-point multiplier based on the IEEE 754 standard.
N-channel Multiplexed FIR Filter
FIR_NTAP_MUX is an N-channel multiplexed FIR filter designed for high sample rate applications where hardware resources are limit…
IIR Filter Second-Order-Section
2nd order IIR filter sometimes referred to as a 'bi-quad'.
Half-band Nyquist Decimation Filter
FIR_DEC_N is a polyphase decimation filter that permits the down sampling of an input signal by any power of 2.
Generic high-speed FIR Filter with symmetry
FIR filter designed for high sample rate applications with symmetrical coefficients and an even or odd number of taps.
Generic ultra-speed FIR Filter
FIR filter designed for very high sample rate applications up to 600 MHz.
Configurable Soft Output Demapper
Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system.
Very High Speed 3GPP LTE Turbo Decoder
This is a very high speed and fully compatible 3GPP LTE turbo decoder with one, two, four or eight parallel MAP decoders.
Fully Configurable Radix 2 FFT/IFFT Processor
ntFFT core is a fully configurable solution that performs the FFT and IFFT transform.
The ntG711_CMP core implements the ITU G.711 compliant compressing.
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm.
Digital I/Q Imbalance correction IP for Wireless Applications
The IQE 100 is a wideband imbalance correction IP, that digitally match in-phase and quadrature signal paths in radio architectur…
High-Performance, Configurable, 8-bit Microcontroller
The R8051XC2 configurable processor core implements a range of fast, 8-bit, micro-controllers that execute the MCS®51 instruction…
High Throughput Additive White Gaussian Noise Generator
A configurable AWGN generator that can be used as emulator of a noisy transmission channel and can support very high throughput r…
ColdFire V1 core with EMAC, Divider and Cryptograhic unit
The synthesizable 32-bit RISC ColdFire V1 Core (CFV1CORE) is the smallest and lowest power processor in the ColdFire family, usin…
Single-channel Cable Modulator
The CMS0021 Single-channel Cable Modulator encodes a transport stream for J83 or DVB-C.
The CMS0035 DVB-Satellite Modulator is an integrated core featuring our DVB-S/-DSNG modulator (CMS0010) and DVB-S2/-S2X modulator…
The CMS0024 Multi-channel Cable Modulator encodes up to four separate transport streams for J83 or DVB-C.
The CMS0008 Viterbi Decoder core implements Viterbi’s algorithm for maximum likelihood decoding of non-feedback convolutional cod…