Overview
The Cadence® Tensilica® NNE 110 offers an energy-efficient hardware-based AI engine that can be paired with a Tensilica based DSP. The NNE 110 targets a variety of applications including audio, voice, and speech AI, lightweight vision AI, and always-on multi-sensory applications.
The product architecture natively supports the most common network layers found in these applications including convolution, depth-wise separable convolution, fully connected, LSTM, pooling, reshaping, and concatenation layers. Other layers can be supported (and further accelerated using TIE) using the host Tensilica DSP. The NNE 110 provides performance scalability from 32 to 128 MACs for 8x8-bit MAC computation, suiting a variety of low-power AI needs. It offers unique features for AI enhancement including hardware-based sparsity for compute and bandwidth reduction as well as on the-fly weight decompression for smaller system footprints.
Learn more about Edge AI Accelerator IP core
The multi-year agreement builds on the companies' existing collaboration and expands Cadence's role in enabling AI-scale semiconductor development on Samsung Foundry's second-generation 2nm platform.
In this second blog of our ongoing series, we examine how Cadence, in close partnership with TSMC, helps teams accelerate AI silicon design at advanced process nodes. For customers, this translates into reduced design risk, faster convergence to tapeout‑quality results, and greater confidence at the leading edge of AI and HPC design.
The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital and custom design enablement, advanced packaging support, and power delivery-optimized flows for AI, HPC, mobile, and future aerospace applications.
Passing PCI Express (PCIe) compliance is different from being ready for the field. A PCIe link can clear every test in a controlled lab environment and still develop margin problems six months into deployment.
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.
Modern compute systems have evolved beyond reliance on a single dominant interface. Today, they're increasingly defined by their ability to support multiple high-speed protocols concurrently—including PCIe, Ethernet, and others. This shift toward multi-protocol capability is fundamentally reshaping how we architect intelligent edge AI systems, especially as inferencing workloads grow more distributed, data-intensive, and latency-sensitive.
