Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
Andes Technology Corp.
Category:
CPU
Compact and Performance Efficiency 32-bit RISC-V Core
The AndesCore™ N225 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with sm…
Overview
The AndesCore™ N225 is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with small gate count, and some dual-issue ability. In addition to commonly used RISC-V IMAC it supports the recently ratified ISA extensions such as B (bit manipulation) and Zce (code size reduction). The N225 implements ePMP to improve core security; and Andes V5 extensions that includes StackSafe™ (for hardware stack protection), CoDense™, PowerBrake and WFI/WFE. The N225 supports both four-wire and two-wire JTAG debug and instruction trace interface for software development. On the performance front, it deploys several configurable options such as dynamic branch prediction, local memories, multiplier optimized for performance or area. Instruction cache or read-only data access is supported with an external cache controller. Moreover, it comes with rich features to ease SoC integration such as CLIC and PLIC for interrupt handling; an AHB-Lite system bus and an AHB-lite low-latency interface; an APB bus for CPU local peripherals, and an AHB-Lite local memory access port for external bus masters.
Key features
- AndeStar™ V5 Instruction Set Architecture (ISA)
- Compliant with RISC-V I, M, A, C, B and Zce extensions
- Andes extensions for performance and code size enhancements
- 3-stage pipeline optimized for gate count and efficiency
- 16/32-bit mixable instructions for code density
- Instruction and read-only caches supported with an external flash controller
- Branch prediction to speed up control code
- Enhanced Physical Memory Protection (ePMP) to enhance core security
- Core-Local Interrupt Controller (CLIC) for fast response, interrupt prioritization and pre-emption and Platform-Level Interrupt Controller (PLIC) for a wide range of cores and system event scenarios
- Patented CoDense™ technology to compress program code on top of the 16-bit extension
- Instruction Trace Interface supports RISC-V Processor Trace v2.0
- StakeSafe™ hardware to measure stack size, and detect runtime overflow/underflow
- PowerBrake, WFI/WFE (Wait For Interrupt/Event) for power management on different occasions
Block Diagram
AndesCore™ N225 block diagram
Applications
- Embedded controller
- Sensor fusion
- Small IoT devices
- Wearable devices
- Smart home
Specifications
Identity
Part Number
AndesCore™ N225
Vendor
Andes Technology Corp.
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
R.O.C
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Frequently asked questions about CPU IP cores
What is Compact and Performance Efficiency 32-bit RISC-V Core?
Compact and Performance Efficiency 32-bit RISC-V Core is a CPU IP core from Andes Technology Corp. listed on Semi IP Hub.
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Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
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Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.