Vendor: WASIELA Category: Channel Coding

LDPC Decoder IS-GPS-800D

The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parit…

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Overview

The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forward Error Correction (FEC). Subframe 2 has a total of 600 bits and subframe 3 has a total of 274 bits. Both subframes are separately encoded using rate 1/2 LDPC codes. In effect, there are 1200 symbols (coded bits) for subframe 2, and 548 symbols (coded bits) for subframe 3.

The VK3061 LDPC IP implements the error correction module in the GPS receiver, as well as the memories. It integrates the de-interleaver, subframe 2 LDPC decoder and subframe 3 LDPC decoder with both the DPRAM and the FIFO. The block diagram for the LDPC IP is shown in the Figure. 1.

Key features

  • Irregular parity check matrix
  • Layered Decoding
  • Minimum sum algorithm
  • Configurable number of iterations
  • Soft decision decoding
  • IS-GPS-800D compliant

Block Diagram

LDPC Decoder IS-GPS-800D block diagram

Applications

  • IS-GPS-800D applications

What’s Included?

  • Synthesizable Verilog
  • System Model (Matlab) and documentation
  • Verilog Test Benches
  • Documentation

Specifications

Identity

Part Number
LDPC Decoder IS-GPS-800D
Vendor
WASIELA
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

WASIELA
HQ: Egypt
Contact WASIELA

Learn more about Channel Coding IP core

Practical Considerations of LDPC Decoder Design in Communications Systems

This paper covers some practical aspects of designing the LDPC decoder starting from comparison between different techniques, different decoders parameters or standards, the effect of those parameters on the LDPC performance, also it discusses the algorithm selection process, and floating point implementation process.

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Frequently asked questions about Channel Coding IP cores

What is LDPC Decoder IS-GPS-800D?

LDPC Decoder IS-GPS-800D is a Channel Coding IP core from WASIELA listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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