Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Stallable pipeline stage with protocol for multiway pipeline fork and join capability
The PIPE is a double register plus a small state machine that enables a fully synchronous stall-able pipeline to be built.
Scalable and Programmable Co-processor
Simpulse’s Pulsar DSP IP Core is a scalable and programmable co-processor for the signal processing of complex embedded digital s…
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream.
Digital IIR filter with APB interface
A range of 5th to 11th order digital IIR filters for conditioning and optionally decimating data from an external source and to D…
LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encodi…
Digital signal processing has been widely used in the area of sensor devices, smart meter, biometrics, communication, Audio, spee…
Convolutional FEC codes are very popular because of their error correction capability and are especially suited for correcting ra…
In Digital video broadcasting for terrestrial broadcasting systems, a FEC sub-system is needed.
The MVD ATSC core is a drop-in module for FPGA that includes the following functions: - Input data framer from DVB-SPI source (MP…
The block consists of 4 low pass filters connected in serially.
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer.
Maximum normalised correlation core
The eSi-MNC core provides the control and data plane interfaces to a Maximum Normalised Correlation module.
Nand Flash write cycles are limited.
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator.
66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3a…
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements.
The VK-402 searches only within a fixed number of lattice points, where the number of considered lattice points decreases as we d…
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the inpu…
The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC).