What is ACU100 Audio Computing IP?
ACU100 Audio Computing IP is a DSP Core IP core from Acute Design listed on Semi IP Hub.
Vendor:
Acute Design
Category:
DSP Core
ACU100 Audio Computing IP
Programmable RISC-V based audio computing IP for deterministic sample-by-sample processing up to 768 kHz.
Overview
ACU100 is a programmable audio computing IP for real-time, sample-based time-domain processing. A scalable cluster of 32-bit RISC-V cores, tightly coupled memories and hardware task/data dispatch implements low-latency audio and any sample based graphs. It supports ANC, transparency, hearing enhancement, EQ, voice processing and multichannel audio pipelines while allowing coefficients, gains, routing and graph branches to change at runtime.
ACU100 Specifications
| Attribute | Specification |
|---|---|
| IP type | Programmable digital audio computing subsystem |
| Compute | 32-bit RISC-V; up to 16 cores; RV32IMA + Zfinx and ACUTE audio extensions |
| Numeric processing | IEEE-754 FP32; fixed/floating-point conversion at graph boundaries |
| Processing mode | Data-triggered sample-based time-domain execution |
| Streaming performance | Up to 768 kHz; graph-processing latency down to approximately 1.3 µs |
| Memory | Configurable TCDM/TCPM capacities and banking |
| Audio and host interfaces | PCM/PDM input and output; memory streams; AHB or AXI host-bus options |
| Runtime controls | Runtime level reconfigurable coefficients, gains, routing, branches and source states |
The supported audio graph complexity and filter orders depend on the configured number of processing cores, memory capacity and ACU100 clock frequency.
Availability and validation
| Status | Description |
|---|---|
| Availability | Ready to be integrated. SDK completed and integrated by customers. |
| Completed validation | RTL verification completed. |
| Customer implementation | Integrated into designs taped out by two customers. |
| Planned milestones | Contact ACUTE Design for the current roadmap; no public dates are stated here. |
Key features
- Configurable RISC-V cluster with up to 16 cores, RV32IMA and Zfinx-based IEEE-754 FP32 processing.
- Data-triggered, deterministic streaming execution with per-core and subsystem clock gating.
- Real-time sample rates up to 768 kHz; graph-processing latency down to approximately 1.3 µs for suitable graphs and configurations.
- Configurable TCDM and TCPM, PCM and PDM input/output, and memory-stream interfaces.
- Python graph description, optimized C processing kernels and runtime-safe graph reconfiguration.
Block Diagram
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Benefits
ACU100’s fully programmable architecture lets developers design their own audio signal paths, implement new filters and deploy custom audio algorithms. Processing topologies and algorithms can evolve in software, giving customers the flexibility to differentiate their designs and support new audio modes. Configurable compute and memory resources allow implementations to scale with algorithm complexity and system budgets. As a fully digital IP, ACU100 is independent of any specific process technology or foundry, giving customers the freedom to choose the manufacturing platform that best fits their product requirements.
Applications
Time-domain audio processing across hearables and wearable audio devices, including adaptive active noise cancellation (ANC), transparency, time-domain beamforming, hearing enhancement, equalization and custom audio processing chains.
What’s Included?
Deliverables include an IP integration package, supporting technical documentation and a software development kit (SDK).
The SDK includes the compiler toolchain, graph development and configuration tools, runtime support and processing libraries. A bit-accurate virtual platform enables developers to develop, simulate and functionally validate their application software and processing graphs.
The IP delivery format and package scope are agreed according to each project’s requirements.
Specifications
Identity
Part Number
ACU100
Vendor
Acute Design
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
France
Frequently asked questions about DSP Core IP cores
How should engineers evaluate this DSP Core?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.