IEEE 802.3bj Reed-Solomon Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic.
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Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
IEEE 802.3bj Reed-Solomon Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic.
Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry- LDPC error correction in a low-power, small-footprint, high-reliability …
The DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on FPGAs …
The transform computation is based on a new matrix formulation of the discreet Fourier transform1 (DFT) which decomposes it into …
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
Variable FFT (run time choice of FFT size)
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
LTE Single Carrier FFT Circuit
Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols.
The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.
ASIP-2 Programmable Filter Engine
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
WCDMA Release 9 compliant Viterbi Decoder
The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the…
Constant False Alarm Rate Processor (CFAR)
The eSi-CFAR is an high throughput Constant False Alarm Rate (CFAR) IP core, whose main application area is automotive driver ass…
High bit rate Turbo Decoder core for 3GPP LTE/ LTE A
The Lekha IP – 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel com…
LMS Adaptive Channel Equalizer
The AH1001_LEQ LMS Adaptive Channel Equalizer (LEQ) FPGA core provides a 17-tap Least Mean Squares (LMS) signed-error adaptive Ch…
32-bit Floating-point Square-root IP Core
High-speed fully pipelined 32-bit floating-point square-root function based on the IEEE 754 standard.
Generic Open Source Viterbi Decoder
Convolutional codes are widely adopted in wireless communication systems for forward error correction.
The BCH decoder has four main functional blocks along with memory blocks.
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-low area and energy cost
Shaped Offset Quadrature Phase Shift Keying - Telemetry Group (SOQPSK-TG) is a type of QPSK/OQPSK modulation.
The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware.
The K-best decoder is part of the MIMO decoder.