Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
DVB-S2X LDPC/BCH Decoder IP (Silicon Proven)
The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single outpu…
DVB-S2X WideBand Demodulator IP
This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integra…
DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven)
This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integra…
The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm.
The AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel.
CCSDS SCCC Turbo Encoder and Decoder
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC).
5G NR is the mobile broadband standard of the 5th generation.
Generic Polar FEC Encoder and Decoder
Polar codes are a trending family of forward error correction codes currently gaining a place in the realm of digital communicati…
DVB-S2/S Demodulator and Decoder IP (Silicon Proven)
The DVB-S2/S Demodulator IP core is a silicon-proven IP core extracted from Production chips.
The DVB-RCS2 modulator is a low-complexity high-performance solution that allows for symbol rates of up to 160 MSymb/s on FPGAs.
A Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems.
Floating-point (IEEE 754) IP based on Arria 10 and Stratix 10 FPGAs
This circuit uses Altera’s new Arria and Stratix 10 FPGAs with hardwired support for floating-point operations (IEEE754).
The Wideband Digital Down Converter (DDC) digitally converts the input signal at IF frequency down to baseband by multiplying inp…
DVB-S2X Wideband BCH and LDPC Decoder
The DVB-S2X wideband decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 500 Msymb/s on FPGAs.
The DVB-S2X wideband modulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s (4…
The DVB-S2X Wideband demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 500 MSymb/s …
FlexDPD is a mature, flexible and solution for the linearization of RF Power Amplifiers (PA).
CCSDS AR4JA LDPC Encoder & Decoder
The CCSDS AR4JA LDPC IP support the LDPC coding schemes as defined by the CCSDS standard.
DisplayPort 1.4 FEC Receiver (Rx)
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified …
Fully Configurable LDPC Encoder
In channel coding redundancy is inserted in the transmitted information bit-stream.