DVB-S2 BCH and LDPC Encoder and Decoder

DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites. It was published in 2005, being the first standard of the second generation DVB standards (DVB-S2/DVB-T2/DVB-C2). Because of its capacity-approaching forward error correction, today DVB-S2 is the de-facto standard in satellite communication and other applications. The Creonic DVB-S2 IP core integrates the forward error correction as defined by the standard (including LDPC and BCH decoder).

• Compliant with ETSI 302 307 V1.2.1 (2009-08) (DVB-S2).
• Support for short blocks (16200 bits) and long blocks (64800 bits).
• Support for all modulation schemes (QPSK, 8-PSK, 16-APSK, 32-APSK).
• Support for all interleaving schemes of all modulation schemes.
• Support for all LDPC and BCH codes as defined by the standard.

• Key features of the decoder are:
  • Soft-Decision demapper, block deinterleaver, LDPC decoder, BCH decoder, descrambler, and CRC check included
  • Low-power and low-complexity design
  • Frame-to-frame on-the-fly configuration
  • AXI4-Stream handshaking interfaces for seamless integration
  • Design-time configuration of throughput for optimal resource utilization
  • Faster convergence due to layered LDPC decoder architecture
  • Early stopping criterion for iterative LDPC decoder, saving a considerable amount of energy
  • Configurable amount of LDPC decoding iterations for trading-off throughput and error correction performance
  • Collection of statistic information (number of modified bits, number of iterations, decode success)  
• Key features of the encoder are:
  • Scrambler, BCH encoder, LDPC encoder, and block interleaver included
  • Low-power and low-complexity design
  • Frame-to-frame on-the-fly configuration
  • AXI4-Stream handshaking interfaces for seamless integration
  • Design-time configuration of throughput for optimal resource utilization.
• Available for ASIC and FPGAs (AMD Xilinx, Intel, Microchip)
• Deliverable includes VHDL source code or synthesized netlist, VHDL testbench, and bit-accurate Matlab, C or C++ simulation model

• Satellite communication
  • Digital Video Broadcasting
  • Interactive Services
  • Professional Services
  • News Gathering
• Applications with the highest
  demands on forward error correction
• Applications with the need for a wide
  range of code rates (1/5 to 9/10)

• VHDL source code or synthesized netlist
• HDL simulation models e.g. for Aldec’s Riviera-PRO
• VHDL testbench
• Bit-accurate Matlab, C or C++ simulation model
• Comprehensive documentation