Programmable OFDM Channel Estimator
The wideband OFDM signal suffers from frequency selective fading.
- TSMC
- 180nm
- BCDG2
- Silicon Proven
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
Programmable OFDM Channel Estimator
The wideband OFDM signal suffers from frequency selective fading.
The DVB-S2X modulator is a low-complexity high-performance solution that allows for symbol rates of up to 250 MSymb/s (2 Gbit/s f…
PMCC_XCM_64x64_D IP block is a low-power array of 1GHz clocked Cross-Correlator cells that are synchronously acquiring two sets o…
Cross-Correlator With 64x2 Channels
PMCC_XCM_64x64 is an IP block capable of calculating the cross-correlations between 64x2 analog signals supplied to the inputs AR…
DOCSIS 3.1 LDPC Decoder (PLC / NCP / Data)
Data Over Cable Service Interface Specification (DOCSIS) is an international telecommunications standard that permits the additio…
Chroma Re-sampler core can be used as chroma sub sampling or chroma up sampling.
LTE and LTE (LTE-A) are the mobile broadband standard of the 4th generation.
Single precision fixed-size streaming floating-point FFT
This FFT circuit employs unique architectural characteristics providing functionality and capabilities not possible with other FF…
CCSDS LDPC Encoder and Decoder
The CCSDS LDPC IP cores support the LDPC coding scheme as defined by the CCSDS standard.
IEEE 802.3bj Reed-Solomon Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic.
Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry- LDPC error correction in a low-power, small-footprint, high-reliability …
The DVB-S2X demodulator is a low-complexity high-performance solution that allows for symbol rates of up to 100 MSymb/s on FPGAs …
The transform computation is based on a new matrix formulation of the discreet Fourier transform1 (DFT) which decomposes it into …
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
Variable FFT (run time choice of FFT size)
This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.
LTE Single Carrier FFT Circuit
Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols.
The DVB-S2X decoder is a silicon-proven, scalable solution that allows for symbol rates of up to 100 MSymbols/s on FPGAs.
ASIP-2 Programmable Filter Engine
Application Specific Instruction Set Processors (ASIPs) possess an instruction set which is tailored to benefit a specific applic…
WCDMA Release 9 compliant Viterbi Decoder
The Lekha IP – 3GPP WCDMA Viterbi Decoder IP Core V1.0 addresses the implementation of the Viterbi Decoder defined as part of the…
DVB-S2 (Digital Video Broadcast – Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmi…