Automotive silicon in the era of AI, functional safety, and cybersecurity
Functional safety must be addressed alongside cybersecurity and AI from the earliest stages of silicon design.
Vendor:
EnSilica
Category:
DSP Core
Constant False Alarm Rate Processor (CFAR)
The eSi-CFAR is an high throughput Constant False Alarm Rate (CFAR) IP core, whose main application area is automotive driver ass…
Overview
The eSi-CFAR is an high throughput Constant False Alarm Rate (CFAR) IP core, whose main application area is automotive driver assistance radar. It is normally applied post-FFT in order to scan output bins for objects in noise, with a pre-designed False Alarm (FA) probability. Pre-screening the FFT output bins in hardware reduces substantially the size of data transfers to the embedded processing system, and equally reduces computationally intensive embedded processing load.
Key features
- Single clock cycle processing per bin making it suitable for interfacing with Pipelined FFT cores.
- Parameterised input I/Q sample bit widths
- Single clock cycle sorting update algorithm for extracting ordered statistics;
- Real-time (per block) configuration of algorithm parameters;
- Parameterised input linear power samples (max 64 bits).
- Version for logarithmic domain for reduced area and power use
- Generalised Ordered Statistic (GOS) CFAR algorithms
- GOS Cell Averaging (CA) – CFAR;
- GOS Greatest Of (GO) – CFAR;
- GOS Smallest Of (SO) – CFAR;
- Cell Averaing (CA) CFAR algorithms
- Classical CA – CFAR;
- Greatest of (GO) CA - CFAR;
- Smallest of (SO) CA – CFAR;
- Cell Averaging Statistic Hofele (CASH) CFAR algorithms
- Concurrent operation of CASH/CA-CFAR core and GOS-CFAR core
- Conversion of linear input power samples in log2 (16-bit) domain
- Real-time configuration of algorithm parameters.
- Equivalent processing in logarithmic domain for reduced area and power use.
- AMBA 4 APB/AXI4-streaming interface
Block Diagram
eSi-CFAR block diagram
Benefits
- Removes a compute intensive task away from the microprocessor to a predictable, low-latency offload engine
- Enables more radar elements to be processed for greater driver security
- Portable to either ASIC or FPGA target architecture
- Silicon proven in ISO-26262 certified products
Applications
- Automotive driver assistance radar
- Roadside traffic management radar
- Military radar
What’s Included?
- RTL
- Testbench
- Synthesis scripts
- Documentation
- MATLAB and C++ bit exact model
- CUDA accelerated bit exact model
Specifications
Identity
Part Number
eSi-CFAR
Vendor
EnSilica
Type
Silicon IP
Provider
HQ:
UK
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Frequently asked questions about DSP Core IP cores
What is Constant False Alarm Rate Processor (CFAR)?
Constant False Alarm Rate Processor (CFAR) is a DSP Core IP core from EnSilica listed on Semi IP Hub.
How should engineers evaluate this DSP Core?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DSP Core IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.