Vendor: Xilinx, Inc. Category: Arithmetic Units

Multiply Adder

The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third ope…

Overview

The Multiply Adder IP performs a multiplication of two operands and adds (or subtracts) the full-precision product to a third operand.The Multiply Adder IP is implemented using Xtreme DSP™ slices and operates on signed or unsigned data.

Key features

  • Supports twos complement-signed and unsigned operations
  • Supports multiplier inputs ranging from 1 to 52 bits unsigned or 2 to 53 bits signed and an add or subtract operand input ranging from 1 to 105 bits unsigned or 2 to 106 bits signed
  • Optional pipelined operation

Specifications

Identity

Part Number
Multiply Adder
Vendor
Xilinx, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Xilinx, Inc.
HQ: USA

Learn more about Arithmetic Units IP core

Implementing matrix inversions in fixed-point hardware

We implement fixed-point matrix inversion on a Virtex-4 FPGA using a synthesizable QR-decomposition MATLAB model and the AccelDSP Synthesis tool. The resulting function occupies 12% of a XC4VSX55 device and has a 1.7 MSPS data rate.

Frequently asked questions about Arithmetic Unit IP cores

What is Multiply Adder?

Multiply Adder is a Arithmetic Units IP core from Xilinx, Inc. listed on Semi IP Hub.

How should engineers evaluate this Arithmetic Units?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Arithmetic Units IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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