The IPrium-DVB-S2X-Modulator IP Core implements the DVB-S2X modulation standard ETSI 302 307-2.
- Modulation Demodulation
- Silicon proven
- Now
- ETSI 302 307-2
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
The IPrium-DVB-S2X-Modulator IP Core implements the DVB-S2X modulation standard ETSI 302 307-2.
The IPrium-DVB-CID-Modulator IP Core implements the modulation standard ETSI TS 103 129 V1.1.1 (2013-05) DVB-CID.
10G I.9 BCH Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.9-BCH-Codec IP core implements "two interleaved extended BCH" super-FEC code for optical lines and is fully comp…
10G/40G RS(255,239) Encoder/Decoder for ITU G.709
The IPrium-10G-G.709-Codec IP Core implements the error-correcting coding Reed-Solomon (255, 239) for the ITU-T G.709 recommendat…
RS-QPSK Modem with low latency
The IPrium-RS-QPSK Modem IP Core is a BPSK/QPSK modem with integrated Reed-Solomon Forward Error Correction (FEC) and is optimize…
Wideband Digital Down Converter (Digital DDC)
The IPrium-Wideband-DDC IP core is full-featured wideband digital downconverter and includes complex digital mixer and digital de…
The IPrium-DVB-CID-Demodulator IP Core is high performance, wide bandwidth digital solution for detection and identification of s…
The IPrium-Viterbi-Decoder IP Core implements Viterbi decoding algorithm and supports trellis mode of operattion.
The IPrium-PSK-Demodulator IP Core implements PSK signal demodulation using Costas and Gardner schemes.
The IPrium-DVB-C-Modulator IP Core is 32-channel DVB-C Modualtor with MAX5861 (MAX5862) support.
1024 State 3GPP2 Viterbi Decoder
The VA10V is a 1024 state error control decoder using the maximum likelihood Viterbi algorithm.
10G I.6 LDPC Encoder/Decoder for ITU G.975.1
The IPrium-10G-I.6-LDPC-Codec IP core implements the LDPC (32640, 30592) forward error correction algorithm for optical lines and…
64 State 4x8PSK (4D 8PSK) CCSDS ECSS Viterbi Decoder
The VA06C is a fully parallel 64 state error control decoder using the maximum likelihood Viterbi algorithm for the 4x8PSK (4D 8P…
DVB-RCS and IEEE 802.16 WiMAX turbo encoder
This is an 8 state DVB-RCS and IEEE 802.16 WiMAX compatible parallel concatenated turbo encoder.
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium…
TETRA-TEDS Turbo Decoder with Optional Viterbi Decoder
This is a fully compatible TETRA-TEDS error control decoder.
Behavioral knowledge space combination rule core with parallel operation
So_ip_ecr_bks_p core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Behavioral knowledge space combination rule core with serial operation
So_ip_ecr_bks_s core can be used to implement the Behavior Knowledge Space (BKS) combination rule to calculate the ensemble class…
Weighted majority voting combination rule core with parallel operation
So_ip_ecr_mvt_p core can be used to implement the Weighted Majority Voting combination rule to calculate the ensemble classificat…
Majority voting combination rule core with parallel operation
So_ip_ecr_mv_p core can be used to implement several Majority Voting combination rules to calculate the ensemble classification o…