Vendor: IP Cores, Inc. Category: Channel Coding

G.9960 LDPC Decoder

LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encodi…

Overview

LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in the ITU G.9960 standard..

Key features

  • parameterized input data width 5-8 bit
  • parameterized internal data width 7-12 bit
  • nearly floating point performance with quantization of 6 input bits and internal computation in 10 bits (less than 0.3 dB from floating point BP with 50 iterations);
  • early stop detection unit ;
  • bit-LLR input
  • Decoder throughput with 10 iterations at 400 MHz clock frequency is listed in the Table 1 below
  • Decoder area:
    • 240K gates
    • 224 DPRAM 128x16
    • 128 DPRAM 32x16
    • 48 ROM 16x64
  • Encoder area:
    • 40K gates
    • 40 Kbit DPRAM
    • 50 Kbit ROM

Benefits

  • Technology Independent
  • Fully Synchronous Design
  • Highly Modular Design with clearly defined interfaces
  • Scan friendly RTL

What’s Included?

  • Synthesizable Verilog RTL source code (VHDL option available)
  • Verilog Testbench
  • Vectors for Testbench
  • Expected results
  • User Documentation

Specifications

Identity

Part Number
LDPC-G9960D
Vendor
IP Cores, Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

IP Cores, Inc.
HQ: USA

Frequently asked questions about Channel Coding IP cores

What is G.9960 LDPC Decoder?

G.9960 LDPC Decoder is a Channel Coding IP core from IP Cores, Inc. listed on Semi IP Hub.

How should engineers evaluate this Channel Coding?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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