66/2112 Codec for Cyclic Code (2112,2080)
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3a…
Overview
The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethernet) standard and IEEE 802.3ba (40 Gbps/100 Gbps operation). The encoder and decoder functions are completely independent and packaged as two sub-cores, CEC1-66/2112E and CEC1-66/2112D respectively. Decoder corrects a single burst error of upto 11 bits.
Key features
- Small Size
- Implements FEC Sublayer for 10GBASE-R (section 74 of the IEEE 802.3 standard)
- 10G/40G/100G Ethernet MAC-friendly interface
- Practically self-contained: requires only memory for one 2112-bit block in the decoder.
- Flow-through design; low latency
Block Diagram
Applications
- 10/40/100G Ethernet MAC
What’s Included?
- Synthesizable Verilog RTL source code (VHDL option available)
- Verilog Testbench
- Vectors for Testbench
- Expected results
- User Documentation
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Channel Coding IP cores
What is 66/2112 Codec for Cyclic Code (2112,2080)?
66/2112 Codec for Cyclic Code (2112,2080) is a Channel Coding IP core from IP Cores, Inc. listed on Semi IP Hub.
How should engineers evaluate this Channel Coding?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Channel Coding IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.