Overview
This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equivalent to 32 ACS units, decoding a single message bit per clock cycle. The high throughput version instances 2 fully parallel stages, equivalent to 64 ACS units, and an interleaved traceback memory architecture. This decoder produces 2 message bits per clock cycle, twice that of conventional Viterbi decoders.
The core can be used for streaming or packetised data applications. By using signed LLR input data it naturally supports de-puncturing by inserting zeros.
The traceback operates by performing a 64-bit block decode after a specified traceback length, and then moving forward a block length and repeating. In this way a high througput is maintained with low memory access requirements.
The traceback memory requirements are significantly lower than other Viterbi decoders, by implementing a novel architecture.
Learn more about Channel Coding IP core
As Low Earth Orbit (LEO) satellite networks target mass-market broadband, mobility and enterprise services, the chipset inside the user terminal – not only the constellation in orbit –will determine the achievable cost, power consumption and production scale
The centre initially plans to recruit 20 specialist modem and mmWave engineers over the next six months, expanding EnSilica’s engineering presence in the European Union and enabling closer participation in European space, semiconductor and communications initiatives.
Europe can strengthen semiconductor sovereignty by investing beyond fabs in design, IP, skilled talent, and product companies.
EnSilica plc , a leading fabless microchip maker with a growing portfolio of reusable IP, serving the Space & Comms, Industrial, Automotive and Healthcare markets, is pleased to announce a new 7 year manufacturing and supply contract to produce an Arm based sensing chip for a German manufacturer of automotive components.
Functional safety must be addressed alongside cybersecurity and AI from the earliest stages of silicon design.
EnSilica is pleased to announce its participation in the newly formed CHERI Adoption Collective, launched by PA Consulting in collaboration with the Department for Science, Innovation & Technology (“DSIT”).
