Processor Architecture for High Performance Video Decode
Processor Architecture for High Performance Video Decode
Vendor:
EnSilica
Category:
Filters Transforms
Digital Down Converter core
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer.
Overview
The eSi-DDC is a Digital Down Converter combining a Digital Frequency Synthesizer (DDS) with a Digital Mixer. The DDS is implemented in a resource efficient way achieving a 16x table compression. The core has an APB interface to set the frequency and phase and the data path uses AXI4-Stream interfaces for simple connectivity.
Key features
- Parameterizable core with these defaults
- 24-bit phase accumulator
- 4096 entry (equivalent) sine/cosine table
- 10-bit sine/cosine table amplitude quantization
- 16-bit input/output data
- APB interface for the control plane
- AXI4-Stream interface for the data plane
Benefits
- Standard interfacing
- Highly compressed DDS table
- Replaces FPGA vendor IP when doing an FPGA to ASIC migration
- ASIC and FPGA target neutral
Applications
- Remote Radio Heads (RRH)
- MIMO Beamformers for 5G
- Front-end for Software Defined Radios (SDR)
What’s Included?
- RTL
- Testbench
- Synthesis scripts
- Documentation
- MATLAB and C++ bit exact model
Specifications
Identity
Part Number
eSi-DDC
Vendor
EnSilica
Type
Silicon IP
Provider
HQ:
UK
Learn more about Filters Transforms IP core
No size fits all for signal processing on FPGA (RF Engines)
No size fits all for signal processing on FPGA (RF Engines)
Employing general-purpose processors for radio DSP
Employing general-purpose processors for radio DSP
Do's and Don'ts of Architecting the Right FPGA Solution for DSP Design
Finally a Practical ''Do and Don't'' primer on architecting FPGA solutions for DSP design. With more do's than don’ts, the article is a down-to-basics look at how to avoid the pitfalls and realize device benefits
10 FPGA Design Techniques You Should Know
Regardless of whether you are using VHDL, System Verilog, or a different design capture language, there are a number of universal design techniques with which FPGA engineers should be familiar, from the very simple to the most advanced.
How to implement double-precision floating-point on FPGAs
The real results of a double-precision matrix multiply core that can easily be extended to a full DGEMM benchmark are demonstrated.
Frequently asked questions about Filters and Transforms IP cores
What is Digital Down Converter core?
Digital Down Converter core is a Filters Transforms IP core from EnSilica listed on Semi IP Hub.
How should engineers evaluate this Filters Transforms?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Filters Transforms IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.