What is High Throughput QAM Demapper?
High Throughput QAM Demapper is a Modulation Demodulation IP core from EnSilica listed on Semi IP Hub.
Vendor:
EnSilica
Category:
Modulation Demodulation
High Throughput QAM Demapper
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator.
Overview
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator. The core is capable of accepting a new equalised QAM symbol per clock cycle and generates all the bit-metrics for that symbol after a short latency. The subcarrier QAM modulation is specified each clock cycle to accommodate systems supporting adaptive bit loading. The QAM channel state information (CSI) can be specified on the same clock cycle as the QAM symbol to allow the LLR to be correctly weighted.
Key features
- Supports BPSK, QPSK, 16-QAM, 64-QAM, 256-QAM and 1024-QAM
- Generated Log Likelihood Ratio bit metrics
- Produces up to 10 LLR bit-metrics per clock
- Capable of 1.5G LLRs/sec
- Supports adaptive bit loading
Benefits
- Efficient and flexible implementation
- OFDM throughput of 150M subcarriers/sec or 1.5G LLRs/sec.
- Exceptional internal precision for high order QAM constellations
- Suitable for both ASIC and FPGA implementation.
- Easy to use interface
Applications
- DVB-T(2),
- DVB-S(2)
- 802.11a/n
- 802.16
- HomePlugAV
What’s Included?
- RTL source code
- Testbench
- Synthesis scripts
- MATLAB mod
Specifications
Identity
Part Number
eSi-QAMDemapper
Vendor
EnSilica
Type
Silicon IP
Provider
HQ:
UK
Frequently asked questions about Modulation and Demodulation IP cores
How should engineers evaluate this Modulation Demodulation?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Modulation Demodulation IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.