5G LDPC Decoder
- Channel Coding
Discover DSP and Math IP for digital signal processing, arithmetic acceleration, and compute-intensive algorithms in semiconductor designs. This category includes IP cores optimized for filtering, transforms, vector processing, fixed-point and floating-point computation, and real-time signal manipulation.
Compare DSP and Math IP by processing architecture, supported numeric formats, throughput, latency, programmability, power efficiency, and target application. These IP solutions are widely used in communications, audio, vision, radar, industrial control, AI preprocessing, and embedded compute platforms.
5G LDPC Decoder
5G Polar Decoder
4G/5G Dual Mode Cell Search
LTE Turbo Decoder
LTE Viterbi Decoder
High-precision 16-bit complex digital up-converter / IQ modulator (DUC) with a fully configurable interpolation filter stage.
CPU IP Following the RVA23 Profile, supporting RVV1.0 and all extensions of Vector Crypto
Dubhe-83 CPU IP features a 10+ stage pipeline, 3-issue, and out-of-order pipeline, follows the RVA23 Profile, supports RV64GCBVH,…
Flash Memory LDPC Decoder IP Core
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …
ION 64b66b IP (64b/66b High-speed Serial Interface)
High-speed serial interface achieved using a lightweight protocol ION 64b66b is an IP for high-speed serial interface targeting a…
ION 8b10b IP (8b/10b High-speed Serial Interface)
High-speed serial interface achieved using a lightweight protocol ION 8b10b is a high-speed serial interface targeting applicatio…
In Digital video broadcasting for digital transmission for satellite applications, a FEC (Forward Error Correction) sub-system is…
In the DVB-T2 transmission, the Physical Layer Pipes (PLPs) carries the MPEG-2 Transport Streams (TSs).
The K-best decoder is part of the MIMO decoder.
ISDB-S3-LDPC-BCH Decoder
The designed Single Carrier is working at adjustable sampling rate as low as 83.457 KHz, as high as 56 MHz It supports adjustable…
This core can perform the two dimensional Discrete Cosine Transform (DCT) and its inverse (IDCT) on an 8x8 block of samples.
Adaptive Interactive detection- Per-Survivor Processing
1: CPM Modulator/ Demodulator Data Rate 200kbps to 10 Mbps in steps of 100Kbps Modulation Index Programmable up to 0.5 Baseband F…
The XC23 is the most DSP core available today for communications applications.
Color Space converter & Chroma Resampler- 4:4:4 RGB to 4:2:2 Y’CbCr
The DB1825 Color Space Converter & Chroma Resampler Verilog IP Core transforms 4:4:4 sampled RGB color components to 4:4:4 Y’CbCr…
4:4:4 Y’CbCr to 4:2:2 Y’CbCr Chroma Resampler (ITU-R BT.601)
The DB1820 Chroma Resampler IP Core down converts 4:4:4 Y’CbCr to 4:2:2 Y’CbCr in accordance with the ITU-R BT.601 standard requi…